CHAPTER 10 SERIAL INTERFACE FUNCTION
User’s Manual U15195EJ5V0UD
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10.3.2 Configuration
UART1 is controlled by asynchronous serial interface mode register 10 and 11 (ASIM10 and ASIM11) and
asynchronous serial interface status register 1 (ASIS1). Receive data is held in the receive buffer registers (RXB1
and RXBL1), and transmit data is held in the transmit shift registers (TXS1 and TXSL1).
Figure 10-16 shows the configuration of asynchronous serial interface 1 (UART1).
(1) Asynchronous serial interface mode registers 10, 11 (ASIM10, ASIM11)
The ASIM10 and ASIM11 registers are 8-bit registers that specify the operation of the asynchronous serial
interface.
(2) Asynchronous serial interface status register 1 (ASIS1)
The ASIS1 register consists of a transmission status flag (SOT1), reception status flag (SIR1), a bit (RB8)
that indicates the 9th bit when extension bit addition is enabled, and 3-bit error flags (PE1, FE1, OVE1) that
indicate the error status at reception end.
(3) Reception control parity check
The receive operation is controlled according to the contents set in the ASIM10 and ASIM11 registers. A
check for parity errors is also performed during receive operation, and if an error is detected, a value
corresponding to the error contents is set in the ASIS1 register.
(4) 2-frame continuous reception buffer register (RXB1)/receive buffer register (RXBL1)
RXB1 is a 16-bit (during 2-frame continuous reception, 9-bit extension data reception) buffer register that
holds receive data. During 7 or 8 bit character reception, 0 is stored in the MSB.
For 16-bit access to this register, specify RXB1, and for access to the lower 8 bits, specify RXBL1.
In the reception enabled state, receive data is transferred from the receive shift register to the reception buffer
in synchronization with the completion of shift-in processing of one frame.
A reception completion interrupt request (INTSR1) is generated upon transfer to the reception buffer (when 2-
frame continuous reception is specified, reception buffer transmission of the second frame).
(5) 2-frame continuous transmission shift register (TXS1)/transmit shift registers (TXSL1)
TXS1 is a 9-bit/2-frame continuous transmission processing shift register. Transmission is started by writing
data to this register.
A transmission completion interrupt request (INTST1) is generated in synchronization with the end of
transmission of 1 frame or 2 frames including the TXS1 data.
For 16-bit access to this register, specify TXS1, and for access to the lower 8 bits, specify TXSL1.
(6) Addition of transmission control parity
A transmission operation is controlled by adding a start bit, parity bit, or stop bit to the data that is written to
the TXS1 or TXSL1 register, according to the contents set in the ASIM10, ASIM11 registers.
(7) Selector
The selector selects the serial clock source.
