CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)
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User’s Manual U15195EJ5V0UD
6.12.1 Restrictions on forcible termination of DMA transfer
During the procedure to forcibly terminate DMA transfer using the INITn bit of the DCHCn register, the transfer may
not be terminated and suspended instead even if the INITn bit has been set to 1. Consequently, when the DMA
transfer of the channel that should have been forcibly terminated is resumed, DMA transfer may end after completion
of an unexpected transfer count, generating a DMA transfer end interrupt (INTDMAn) (n = 0 to 3).
[Preventive measures]
The above can be prevented by software using either of the following.
(1) Temporarily stopping transfers of all DMA channels
These restrictions can be prevented if the program configuration is such that the TCn bit of the DCHCn
register is expected to be 1 only during the preventive processing shown below. (The TCn bit of the DCHCn
register is cleared to 0 after a read. That is, the TCn bit is cleared to 0 when preventive processing routine (ii)
in step <5> of the preventive processing is executed.)
<1> Disable interrupts (DI).
<2> Read the DMA restart register (DRST) and transfer the value in the ENn bit of each channel to general-
purpose registers (value A).
<3> Write 00H to the DRST register (write twice
Note
). Writing twice ensures that DMA transfer is stopped
before the processing in step <4>.
<4> Set the INITn bit of the DCHCn register of the channel to be forcibly terminated to 1.
<5> Manipulate value A read in step <2> as follows (value B).
(i) Clear the bit corresponding to the channel to be forcibly terminated to 0.
(ii) If both the TCn bit of the DCHCn register and the ENn bit of the DRST register of the channel that is
not to be forcibly terminated are 1 (the ANDed value is 1), clear the bit corresponding to the channel
to 0.
<6> Write value B manipulated in step <5> to the DRST register.
<7> Enable interrupts (EI).
Note
Write three times if the transfer target (transfer source or destination) is the internal RAM.
Caution Step <5> must be performed to prevent the ENn bit of the DRST register of the channel
for which transfer was successfully complete during steps <2> and <3> from being
illegally set to 1.
Remark
n = 0 to 3
