CHAPTER 10 SERIAL INTERFACE FUNCTION
User’s Manual U15195EJ5V0UD
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(2) Asynchronous serial interface status register 0 (ASIS0)
The ASIS0 register, which consists of 3-bit error flags (PE, FE and OVE), indicates the error status when
UART0 reception is complete.
The ASIS0 register is cleared to 00H by a read operation. When a reception error occurs, receive buffer
register 0 (RXB0) should be read and the error flag should be cleared after the ASIS0 register is read.
This register is read-only, in 8-bit units.
Cautions 1. When the UARTCAE0 bit or RXE0 bit of the ASIM0 register is set to 0, or when the ASIS0
register is read, the PE, FE, and OVE bits of the ASIS0 register are cleared (0).
2. Manipulation using a bit manipulation instruction is prohibited.
7 6 5 4 3 2 1 0
Address
After
reset
ASIS0
0 0 0 0 0 PE
FE
OVE
FFFFFA03H
00H
Bit position
Bit name
Function
2 PE
This is a status flag that indicates a parity error.
0: When the ASIM0 register’s UARTCAE0 and RXE0 bits are both set to 0, or
after the ASIS0 register is read
1: When the receive data parity does not match the parity bit after receive
completion
Caution The operation of the PE bit differs according to the settings of the
PS1 and PS0 bits of the ASIM0 register.
1 FE
This is a status flag that indicates a framing error.
0: When the ASIM0 register’s UARTCAE0 and RXE0 bits are both set to 0, or
after the ASIS0 register is read
1: When no stop bit was detected after receive completion
Caution For receive data stop bits, only the first bit is checked regardless
of the stop bit length.
0 OVE
This is a status flag that indicates an overrun error.
0: When the ASIM0 register’s UARTCAE0 and RXE0 bits are both 0, or after the
ASIS0 register is read.
1: When UART0 completed the next receive operation before reading the
receive data in the RXB0 register.
Caution When an overrun error occurs, the next receive data value is not
written to the RXB0 register and the data is discarded.
