CHAPTER 10 SERIAL INTERFACE FUNCTION
User’s Manual U15195EJ5V0UD
432
(2) Serial clock generation
A serial clock can be generated according to the settings of the CKSR0 and BRGC0 registers.
The base clock to the 8-bit counter is selected by the TPS3 to TPS0 bits of the CKSR0 register.
The 8-bit counter divisor value can be set by the MDL7 to MDL0 bits of the BRGC0 register.
(a) Clock select register 0 (CKSR0)
The CKSR0 register is an 8-bit register for selecting the base clock (f
CLK
) using the TPS3 to TPS0 bits.
The clock selected by the TPS3 to TPS0 bits becomes the base clock (f
CLK
) of the transmission/
reception module.
This register can be read or written in 8-bit units.
Cautions 1. The maximum allowable frequency of the base clock (f
CLK
) is 20 MHz. Therefore,
when the system clock’s frequency is 40 MHz, TPS3 to TPS0 bits cannot be set to
0000B.
At 40 MHz, set the TPS3 to TPS0 bits to a value other than 0000B, and set the
UARTCAE0 bit of the ASIM0 register to 1.
2. Set the UARTCAE0 bit of the ASIM0 register to 0 before rewriting the TPS3 to TPS0
bits.
7 6 5 4 3 2 1 0
Address
After
reset
CKSR0
0 0 0 0
TPS3
TPS2
TPS1
TPS0
FFFFFA06H
00H
Bit position
Bit name
Function
Specifies the base clock (f
CLK
)
TPS3 TPS2 TPS1 TPS0
Base
clock
(f
CLK
)
0 0 0 0
f
XX
0 0 0 1
f
XX
/2
0 0 1 0
f
XX
/4
0 0 1 1
f
XX
/8
0 1 0 0
f
XX
/16
0 1 0 1
f
XX
/32
0 1 1 0
f
XX
/64
0 1 1 1
f
XX
/128
1 0 0 0
f
XX
/256
1 0 0 1
f
XX
/512
1 0 1 0
f
XX
/1,024
1 0 1 1
f
XX
/2,048
1 1
Arbitrary Arbitrary Setting
prohibited
3 to 0
TPS3 to
TPS0
Remark
f
XX
: Internal system clock
