CHAPTER 9 TIMER/COUNTER FUNCTION
264
User’s Manual U15195EJ5V0UD
Figure 9-29. Operation Timing in PWM Mode 1 (Asymmetric Triangular Wave, BFCMnx = CM0n3) (2/2)
(b) Operation timing of compare registers 0n4 and 0n5 (CM0n4, CM0n5)
CM0n3
CM0n3
a
CM0nx
match
CM0nx
match
INTTM0n
INTTM0n
TM0n
count value
BFCMnx
Interrupt request
CM0nx
0000H
b
b
b
b
a
b
a
b
b
b
INTCM0n3
INTCM0n3
INTCM0nx INTCM0nx
INTCM0nx
CM0nx
match
Remarks 1.
n = 0, 1
2.
x = 4, 5
3.
b = CM0n3
4.
INTCM0nx is generated on a match between TM0n and CM0nx (a in the above figure).
Since TM0n and CM0n0 to CM0n2 match is detected during count down of TM0n when BFCMn0 to
BFCMn2 = CM0n3 has been set, the F/F remains reset as is and is not set. Therefore, the positive
phase side (TO0n0, TO0n2, TO0n4 pins) outputs a low level, and the negative phase side (TO0n1,
TO0n3, TO0n5 pins) continues to output a high level. Moreover, the timing of matching with TM0n with
CM0n0 to CM0n2 = CM0n3 is the cycle when transfer is performed from BFCMn0 to BFCMn2 to CM0n0
to CM0n2 by INTCM0n3.
The above explanation applies to an active high case. In an active low case, the levels of positive and
negative phases are merely inverted and other operations remain the same.
