CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)
106
User’s Manual U15195EJ5V0UD
6.2 Configuration
CPU
Internal RAM
On-chip
peripheral I/O
On-chip peripheral I/O bus
Internal bus
Data
control
Address
control
Count
control
Channel
control
DMAC
V850E/IA2
Bus interface
External bus
External
RAM
External
ROM
External I/O
DMA source address
register (DSAnH/DSAnL)
DMA transfer count
register (DBCn)
DMA channel control
register (DCHCn)
DMA destination address
register (DDAnH/DDAnL)
DMA addressing control
register (DADCn)
DMA disable status
register (DDIS)
DMA trigger factor
register (DTFRn)
DMA restart register (DRST)
Remark
n = 0 to 3