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User’s Manual U15195EJ5V0UD
6.12
Forcible Termination .............................................................................................................. 129
6.12.1
Restrictions on forcible termination of DMA transfer ..................................................................130
6.13
Time Required for DMA Transfer .......................................................................................... 131
6.14
Cautions................................................................................................................................... 132
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION..................................................134
7.1
Features ................................................................................................................................... 134
7.2
Non-Maskable Interrupt.......................................................................................................... 138
7.2.1
Operation ...................................................................................................................................139
7.2.2
Restore.......................................................................................................................................141
7.2.3
Non-maskable interrupt status flag (NP) ....................................................................................142
7.2.4
Edge detection function..............................................................................................................142
7.3
Maskable Interrupts ................................................................................................................ 143
7.3.1 Operation ...................................................................................................................................143
7.3.2
Restore.......................................................................................................................................145
7.3.3
Priorities of maskable interrupts .................................................................................................146
7.3.4
Interrupt control register (xxICn).................................................................................................150
7.3.5
Interrupt mask registers 0 to 3 (IMR0 to IMR3) ..........................................................................153
7.3.6
In-service priority register (ISPR) ...............................................................................................154
7.3.7
Maskable interrupt status flag (ID)..............................................................................................155
7.3.8
Interrupt trigger mode selection..................................................................................................155
7.4
Software Exception................................................................................................................. 163
7.4.1
Operation ...................................................................................................................................163
7.4.2
Restore.......................................................................................................................................164
7.4.3
Exception status flag (EP) ..........................................................................................................165
7.5
Exception Trap ........................................................................................................................ 166
7.5.1
Illegal opcode definition..............................................................................................................166
7.5.2
Debug trap .................................................................................................................................168
7.6
Multiple Interrupt Servicing Control ..................................................................................... 170
7.7
Interrupt Response Time........................................................................................................ 172
7.8
Periods in Which CPU Does Not Acknowledge Interrupts ................................................. 173
CHAPTER 8 CLOCK GENERATION FUNCTION ...............................................................................174
8.1 Features ................................................................................................................................... 174
8.2 Configuration .......................................................................................................................... 174
8.3
Input Clock Selection ............................................................................................................. 175
8.3.1 Direct mode ................................................................................................................................175
8.3.2 PLL mode ...................................................................................................................................175
8.3.3
Peripheral command register (PHCMD).....................................................................................176
8.3.4
Clock control register (CKC).......................................................................................................177
8.3.5
Peripheral status register (PHS).................................................................................................179
8.4 PLL
Lockup.............................................................................................................................. 180
8.5 Power
Save
Control ................................................................................................................ 181
8.5.1
Overview ....................................................................................................................................181
8.5.2
Control registers .........................................................................................................................184
8.5.3
HALT mode ................................................................................................................................187
8.5.4
IDLE mode .................................................................................................................................189
