NEC PD703114, User Manual

Page: 647 / 692

CHAPTER 16 ELECTRICAL SPECIFICATIONS
647
User’s Manual U15195EJ5V0UD
(5) Multiplexed bus timing
(a) CLKOUT asynchronous (T
A
= –40 to +85
°
C, REGIN = 3.0 to 3.6 V, V
DD
= RV
DD
= 5.0 V
±
0.5 V,
V
SS3
= V
SS
= CV
SS
= 0 V, output pin load capacitance: C
L
= 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
Address setup time (to ASTB
↓
) t
SAST
<17> (0.5 + w
AS
)T – 16 ns
Address hold time (from ASTB
↓
) t
HSTA
<18> (0.5 + w
AH
)T – 15 ns
Address float delay time from RD
↓
t
FRDA
<19> 11 ns
Data input setup time from address t
SAID
<20> (2 + w + w
AS
+
w
AH
)T – 40
ns
Data input setup time from RD
↓
t
SRDID
<21> (1 + w)T – 40 ns
Delay time from ASTB
↓
to RD, LWR, UWR
↓
t
DSTRDWR
<22> (0.5 + w
AH
)T – 15 ns
Data input hold time (from RD
↑
) t
HRDID
<23> 0 ns
Address output time from RD
↑
t
DRDA
<24> (1 + i)T – 15 ns
Delay time from RD, LWR, UWR
↑
to ASTB
↑
t
DRDWRST
<25> 0.5T – 15 ns
Delay time from RD
↑
to ASTB
↓
t
DRDST
<26> (1.5 + i + w
AS
)T – 15 ns
RD, LWR, UWR low-level width t
WRDWRL
<27> (1 + w)T – 22 ns
ASTB high-level width t
WSTH
<28> (1 + w
AS
)T – 15 ns
Data output time from LWR, UWR
↓
t
DWROD
<29> 10 ns
Data output setup time (to LWR, UWR
↑
) t
SODWR
<30> (1 + w)T – 25 ns
Data output hold time (from LWR, UWR
↑
) t
HWROD
<31> T – 20 ns
t
SAWT1
<32> w
≥
1 (1.5 + w
AS
+
w
AH
)T– 40
ns WAIT data output hold time (to address)
t
SAWT2
<33> (1.5 + w + w
AS
+
w
AH
)T – 40
ns
t
HAWT1
<34> w
≥
1 (0.5 + w + w
AS
+
w
AH
)T
ns WAIT hold time (from address)
t
HAWT2
<35> (1.5 + w + w
AS
+
w
AH
)T
ns
t
SSTWT1
<36> w
≥
1 (1 + w
AH
)T – 32 ns WAIT setup time (to ASTB
↓
)
t
SSTWT2
<37> (1 + w + w
AH
)T – 32 ns
t
HSTWT1
<38> w
≥
1 (w + w
AH
)T ns WAIT hold time (from ASTB
↓
)
t
HSTWT2
<39> (1 + w + w
AH
)T ns
Remarks 1. T = t
CYK
2. w
AS
: Number of address setup wait states (0 or 1)
3. w
AH
: Number of address hold wait states (0 or 1)
4. w: Number of wait clocks inserted in the bus cycle
The sampling timing changes when a programmable wait is inserted.
5. i: Number of idle states inserted after the read cycle (0 or 1)
6. Observe at least one of the data input hold times t
HKID
or
t
HRDID
.
7. To understand how the number of wait cycles to be inserted is determined, refer to 4.6.3 Relationship
between programmable wait and external wait.