CHAPTER 4 BUS CONTROL FUNCTION
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User’s Manual U15195EJ5V0UD
4.4 Bus Cycle Type Control Function
In the V850E/IA2, the following external devices can be connected directly to each memory block.
•
SRAM, external ROM, external I/O
Connected external devices are specified by bus cycle type configuration registers 0 and 1 (BCT0 and BCT1).
(1) Bus cycle type configuration registers 0, 1 (BCT0, BCT1)
These registers can be read/written in 16-bit units.
Only the ME0 bit is valid in the V850E/IA2. These registers are not affected by other bit settings.
Caution Write to the BCT0 and BCT1 registers after reset, and then do not change the set values.
Also, do not access an external memory area other than the one for this initialization
routine until the initial setting of the BCT0 and BCT1 registers is complete. However, it is
possible to access external memory areas whose initial settings are complete.
15
ME3
BCT0
CSn signal
Address
FFFFF480H
After reset
CCCCH
14
1
1
0
0
13
12
11
ME2
10
9
0
0
0
0
8
7
ME1
6
1
5
4
3
ME0
2
1
1
0
0
0
CS3
CS2
CS1
CS0
15
ME7
BCT1
CSn signal
Address
FFFFF482H
After reset
CCCCH
14
1
13
0
0
0
0
12
11
ME6
10
1
9
8
7
ME5
6
1
5
0
0
0
0
4
3
ME4
2
1
1
0
CS6
CS5
CS4
CS7
Bit position
Bit name
Function
Sets memory controller operation enable for each chip select.
MEn
Memory controller operation enable
0
Operation disabled
1
Operation enabled
15, 11, 7, 3
(BCT0),
15, 11, 7, 3
(BCT1)
MEn
(n = 0 to 7)
