CHAPTER 8 CLOCK GENERATION FUNCTION
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User’s Manual U15195EJ5V0UD
Data is set in the clock control register (CKC) according to the following sequence.
<1> Disable interrupts (set the NP bit of PSW to 1)
<2> Prepare data in any one of the general-purpose registers to set in the specific register.
<3> Write arbitrary data to the peripheral command register (PHCMD)
<4> Set the clock control register (CKC) (with the following instructions).
•
Store instruction (ST/SST instruction)
<5> Insert five or more NOP instructions (5 instructions (<5> to <9>))
<10> Release the interrupt disabled state (set the NP bit of PSW to 0).
[Sample coding]
<1>
LDSR rX,
5
<2>
MOV 0X04,
r10
<3>
ST.B r10, PHCMD [r0]
<4>
ST.B r10, CKC [r0]
<5>
NOP
<6>
NOP
<7>
NOP
<8>
NOP
<9>
NOP
<10>
LDSR rY,
5
Remark
rX: Value written to PSW
rY: Value returned to PSW
No special sequence is required to read the specific register.
Cautions 1. If an interrupt is acknowledged between the issuing of data to PHCMD <3> and writing to the
specific register immediately after <4>, the write operation to the specific register is not
performed and a protection error (the PRERR bit of the PHS register = 1) may occur.
Therefore, set the NP bit of the PSW to 1 <1> to disable interrupt acknowledgment. Also
disable interrupt acknowledgment when selecting a bit manipulation instruction for the
specific register setting.
2. Although the data written to the PHCMD register is dummy data, use the same register as
the general-purpose register used in specific register setting <4> for writing to the PHCMD
register (<3>). The same method should be applied when using a general-purpose register
for addressing.
3. Before executing this processing, complete all DMA transfer operations.
