CHAPTER 8 CLOCK GENERATION FUNCTION
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User’s Manual U15195EJ5V0UD
8.3 Input Clock Selection
The clock generator consists of an oscillator and a PLL synthesizer. For example, connecting a 4.0 MHz crystal
resonator or ceramic resonator to the X1 and X2 pins enables a 40 MHz internal system clock (f
XX
) to be generated
when the multiplier is 10. Also, an external clock can be input directly to the oscillator. In this case, the clock signal
should be input only to the X1 pin (the X2 pin should be left open). Two basic operation modes are provided for the
clock generator. These are the PLL mode and the direct mode. The operation mode is selected by the CKSEL pin.
The input to this pin is latched on reset.
CKSEL
Operation Mode
0 PLL
mode
1 Direct
mode
Caution The input level for the CKSEL pin must be fixed. If it is switched during operation, a
malfunction may occur.
8.3.1 Direct mode
In the direct mode, the external clock is divided by two and the divided clock is supplied as the internal system
clock. The maximum frequency that can be input in the direct mode is 50 MHz. This mode is used in application
system where the V850E/IA2 operates at relatively low frequencies.
Caution In direct mode, an external clock must be input (an external resonator should not be
connected).
8.3.2 PLL mode
In PLL mode, an external resonator is connected or external clock is input and multiplied by the PLL synthesizer.
The multiplied PLL output is divided by the division ratio specified by the clock control register (CKC) to generate a
system clock that is 10, 5, 2.5, or 1 times the frequency (f
X
) of the external resonator or external clock.
After reset, an internal system clock (f
XX
) that is 1 time the frequency (1
×
f
X
) of the internal clock frequency (f
X
) is
generated.
When a frequency that is 10 times the clock frequency (f
X
) (10
×
f
X
) is generated, a system with low noise and low
power consumption can be realized because a frequency of up to 40 MHz is obtained based on a 4 MHz external
resonator or external clock.
In PLL mode, if the clock supply from an external resonator or external clock source stops, operation of the internal
system clock (f
XX
) based on the self-propelled frequency of the clock generator’s internal voltage controlled oscillator
(VCO) continues. In this case, f
XX
is undefined. However, do not devise an application method expecting to use this
self-propelled frequency.
Example:
Clocks when PLL mode (f
XX
= 10
×
f
X
) is used
Internal System Clock Frequency (f
XX
)
External Resonator or External Clock Frequency (f
X
)
40.000 MHz
4.0000 MHz
