Freescale Semiconductor PXR4030, Reference Manual

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Deserial Serial Peripheral Interface (DSPI)
Freescale Semiconductor 25-19
PXR40 Microcontroller Reference Manual, Rev. 1
Address: DSP 0x2C Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
TCF
TXRXS 0
EOQF TFUF
0
TFFF
0 0 0 0 0
RFOF
0
RFDF
0
W
Reset 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
TXCTR TXNXTPTR RXCTR POPNXTPTR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 25-6. DSPI Status Register (DSPI_SR)
Table 25-14. DSPI_SR Field Descriptions
Field Description
0
TCF
Transfer Complete Flag. The TCF bit indicates that all bits in a frame have been shifted out. The TCF
bit is set at the end of the frame transfer. The TCF bit remains set until cleared by software.
0 Transfer not complete
1 Transfer complete
1
TXRXS
TX & RX Status. The TXRXS bit reflects the status of the DSPI. See Section 25.4.2, Start and Stop
of DSPI Transfers , for information on how what causes this bit to be negated or asserted.
0 TX and RX operations are disabled (DSPI is in STOPPED state)
1 TX and RX operations are enabled (DSPI is in RUNNING state)
2 Reserved, should be cleared.
3
EOQF
End of Queue Flag. The EOQF bit indicates that transmission in progress is the last entry in a queue.
The EOQF bit is set when TX FIFO entry has the EOQ bit set in the command halfword and the end
of the transfer is reached. The EOQF bit remains set until cleared by software. When the EOQF bit is
set, the TXRXS bit is automatically cleared.
0 EOQ is not set in the executing command
1 EOQ bit is set in the executing SPI command
4
TFUF
Transmit FIFO Underflow Flag. The TFUF bit indicates that an underflow condition in the TX FIFO has
occurred. The transmit underflow condition is detected only for DSPI blocks operating in slave mode
and SPI configuration. The TFUF bit is set when the TX FIFO of a DSPI operating in SPI slave mode
is empty, and a transfer is initiated by an external SPI master. The TFUF bit remains set until cleared
by software.
0 TX FIFO underflow has not occurred
1 TX FIFO underflow has occurred
5 Reserved, should be cleared.
6
TFFF
Transmit FIFO Fill Flag. The TFFF bit provides a method for the DSPI to request more entries to be
added to the TX FIFO. The TFFF bit is set while the TX FIFO is not full. The TFFF bit can be cleared
by host software or an acknowledgement from the DMA controller when the TX FIFO is full.
0 TX FIFO is full
1 TX FIFO is not full
7–11 Reserved, should be cleared.