Freescale Semiconductor PXR4030, Reference Manual

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Interrupts and Interrupt Controller (INTC)
10-40 Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
request, discards the transactions, and flushes the processing pipeline. However, ISR2 cannot access the
data block coherently because the data block is now corrupted.
OSEK uses the GetResource and ReleaseResource system services to manage access to a shared resource.
To prevent corrupting a coherent data block, use the following code to modify the PRI in INTC_CPR.
Interrupts must be enabled before executing the following GetResource code sequence:
GetResource:
raise PRI
mbar
isync
ReleaseResource:
mbar
lower PRI
10.5.5.2.2 Raised Priority Preserved
Before the instruction after the GetResource system service executes, all pending transactions have
completed. These pending transactions can include an ISR for a peripheral or software settable interrupt
request whose priority was equal to or lower than the raised priority. Also, during the epilog of the interrupt
exception handler for this preempting ISR, the raised priority has been restored from the LIFO to PRI in
INTC_CPR. The shared coherent data block now can be accessed coherently.
Figure 10-16 shows the
timing diagram for this scenario, and Table 10-10 explains the events. The example is for software vector
mode, but except for the method of retrieving the vector and acknowledging the interrupt request to the
processor, hardware vector mode is identical.