Freescale Semiconductor PXR4030, Reference Manual

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FlexRay Communication Controller (FLEXRAY)
Freescale Semiconductor 22-123
PXR40 Microcontroller Reference Manual, Rev. 1
The common configuration data given in the section on Specific Configuration Data can not be
reconfigured when the protocol is out of the POC:config state.
22.6.8.1 Reconfiguration Schemes
Depending on the target and destination basic state of the message buffer that is to be reconfigured, there
are three reconfiguration schemes.
22.6.8.1.1 Basic Type Not Changed (RC1)
A reconfiguration will not change the basic type of the individual message buffer, if both the message
buffer transfer direction bit MBCCSn[MTD] and the message buffer type bit MBCCSn[MBT] are not
changed. This type of reconfiguration is denoted by RC1 in
Figure 22-137 . Single transmit and receive
message buffers can be RC1-reconfigured when in the HDis or HDisLck state. Double transmit message
buffers can be RC1-reconfigured if both the transmit side and the commit side are in the HDis state.
22.6.8.1.2 Buffer Type Not Changed (RC2)
A reconfiguration will not change the buffer type of the individual message buffer if the message buffer
buffer type bit MBCCSRn[MBT] is not changed. This type of reconfiguration is denoted by RC2 in
Figure 22-137 . It applies only to single transmit and receive message buffers. Single transmit and receive
message buffers can be RC2-reconfigured when in the HDis or HDisLck state.
22.6.8.1.3 Buffer Type Changed (RC3)
A reconfiguration will change the buffer type of the individual message buffer if the message buffer type
bit MBCCSRn[MBT] is changed. This type of reconfiguration is denoted by RC3 in
Figure 22-137 . The
RC3 reconfiguration splits one double buffer into two single buffers or combines two single buffer into
one double buffer. In the later case, the two single message buffers must have consecutive message buffer
numbers and the smaller one must be even. Message Buffers can be RC3 reconfigured if they are in the
HDis state.
Figure 22-137. Message Buffer Reconfiguration Scheme
22.6.9 Receive FIFOs
This section provides the functional description of the two receive FIFOs.
single RX single TX
double TX (commit side)
double TX (transmit side)
RC1
RC1
RC1
RC2
RC3 RC3