Freescale Semiconductor PXR4030, Reference Manual

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Enhanced Time Processing Unit (eTPU2)
29-86 Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
83 clocks * 25 ns/clock = 2075 ns
Conclusion: in this system configuration PWM can run with a minimum high time or low time of
2075 ns.
Note that in double match eTPU system the PWM can be serviced once in each period, and there is
no latency for minimum high time. The latency in eTPU PWM function will represent the minimum
PWM period.
Finding the WCL for PPWA on Channel 1
The following shows how to find the WCL for PPWA on channel 1.
1. Find the worst-case service time for each active channel. See step 1 of previous example.
2. Assume channel 1 has just been serviced and that channels 0 and 2 are continuously requesting
service. Using the H-M-H-L-H-M-H time-slot sequence, map the channels that are granted for
each time slot. See
Figure 29-40 .
Figure 29-40. Next Servicing for Channel 1
Channel 0 will be serviced twice and channel 2 once before channel 1 is serviced again.
3. Add time for the six-clock CPU time-slot transitions. See Figure 29-40 and Table 29-24 .
131 clocks * 25 ns/clock = 3275 ns
Conclusion: in this system configuration PPWA can measure a period or pulse of minimum 3275
ns.
Table 29-23. Worst-Case Latency for Channel 0
Channel 0 worst-case service time 25 clocks
Channel 1 worst-case service time 46 clocks
Two 6-clock time-slot transitions 12 clocks
Total clocks 83 clocks
Table 29-24. Worst Case Latency for Channel 1
Two Channel 0 worst-case service times 50 clocks
Channel 1 worst-case service time 46 clocks
Channel 2 worst-case service time 11 clocks
Four 6-clock time-slot transitions 24 clocks
Total clocks 131 clocks
TPU CH1 WCL TIM TPU CH1 WCL TIM
CHANNEL
SERVICED
WORST CASE LATENCY
CHANNEL 1
H M H L H M H H
CHANNEL 0
SERVICED
CHANNEL 2
SERVICED
= 10-CYCLE TIME SLOT TRANSITION
= 4-CYCLE NOP INSTRUCTION
CHANNEL 0
SERVICED
CHANNEL 1
SERVICED