Freescale Semiconductor PXR4030, Reference Manual

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FlexCAN Module
Freescale Semiconductor 24-31
PXR40 Microcontroller Reference Manual, Rev. 1
24
BUF7I
Buffer MB7 Interrupt or “FIFO Overflow”
If the FIFO is not enabled, this bit flags the interrupt for MB7. If the FIFO is enabled, this flag indicates an overflow
condition in the FIFO (frame lost because FIFO is full).
0 No such occurrence
1 MB7 completed transmission/reception or FIFO overflow
25
BUF6I
Buffer MB6 Interrupt or “FIFO Warning”
If the FIFO is not enabled, this bit flags the interrupt for MB6. If the FIFO is enabled, this flag indicates that 5 out of
6 buffers of the FIFO are already occupied (FIFO almost full).
0 No such occurrence
1 MB6 completed transmission/reception or FIFO almost full
26
BUF5I
Buffer MB5 Interrupt or “Frames available in FIFO”
If the FIFO is not enabled, this bit flags the interrupt for MB5. If the FIFO is enabled, this flag indicates that at least
one frame is available to be read from the FIFO.
0 No such occurrence
1 MB5 completed transmission/reception or frames available in the FIFO
27–31
BUF4I–B
UF0I
Buffer MB
i
Interrupt or “reserved”
If the FIFO is not enabled, these bits flag the interrupts for MB0 to MB4. If the FIFO is enabled, these flags are not
used and must be considered as reserved locations.
0 No such occurrence
1 Corresponding MB completed transmission/reception
Table 24-16. FLEXCAN_x_IFLAG1 Field Descriptions (continued)
Field Description