Freescale Semiconductor PXR4030, Reference Manual

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Core (e200z7) Overview
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 13-7
22
DCLO
Data Cache Lock Overflow
Indicates a lock overflow (overlocking) condition occurred. This bit is set by hardware
on an “overlocking” condition, and will remain set until cleared by software writing 0 to
this bit location.
23
DCLFC
Data Cache Lock Bits Flash Clear
When written to a ‘1’, a cache lock bits flash clear operation is initiated by hardware.
Once complete, this bit is reset to ‘0’. Writing a ‘1’ while a flash clear operation is in
progress will result in an undefined operation. Writing a ‘0’ to this bit while a flash clear
operation is in progress will be ignored. Cache Lock Bits Flash Clear operations require
approximately 134 cycles to complete. Clearing occurs regardless of the enable (DCE)
value.
24
DCLOA
Data Cache Lock Overflow Allocate
Set by software to allow a lock request to replace a locked line when a lock overflow
situation exists.
0 Indicates a lock overflow condition will not replace an existing locked line with the
requested line
1 Indicates a lock overflow condition will replace an existing locked line with the
requested line
25–26
DCEA
Data Cache Error Action
00 Error Detection causes Machine Check exception.
01 Error Detection causes Correction/Auto-invalidation. No machine check is
generated for uncorrectable errors unless the cache line was locked and invalidated
or is dirty. Dirty lines are not auto-invalidated. In EDC mode, correction is performed
for single-bit tag errors, single-bit lock errors, and single or multi-bit dirty errors. In
parity mode, tag and lock errors will result in invalidation of clean lines. For both
modes, correction is performed for data errors by reloading of the line.
1x Reserved
27 Reserved
1
28
DCBZ32
Data Cache dcba, dcbz, operation length
0 dcba, dcbz, operations operate on an entire cache line
1 dcba, dcbz, operations operate on 32 bytes of a cache line
Note: This bit is implemented for forward compatibility. Since cache lines are 32 bytes,
this bit is ignored for dcba, dcbz, operations
29
DCABT
Data Cache Operation Aborted
Indicates a Cache Invalidate or a Cache Lock Bits Flash Clear operation was aborted
prior to completion. This bit is set by hardware on an aborted condition, and will remain
set until cleared by software writing 0 to this bit location.
Table 13-1. L1CSR0 Field Descriptions (continued)
Field Description