Freescale Semiconductor PXR4030, Reference Manual

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Frequency Modulated Phase-Locked Loop (FMPLL)
6-2 Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
For register and bit descriptions, see:
• Section 7.3.1.27, System Clock Register (SIU_SYSDIV)
• Section 7.3.1.24, External Clock Control Register (SIU_ECCR)
6.1.1 Block Diagram
A simplified block diagram of the FMPLL illustrates the functionality and interdependence of major
blocks (see
Figure 6-2 ). Shaded blocks represent analog circuit components that make up the core analog
portion of the FMPLL. The complete FMPLL closed-loop system contains the feedback divider (EMFD)
and output divider (ERFD). Refer to
Section 6.4.3.3, PLL Normal Mode Without FM, for details on each
sub-block.
Figure 6-2. FMPLL Block Diagram
6.1.2 Features
The FMPLL has these major features (refer to PXR40 Microcontroller Data Sheet for performance data
and restrictions):
• Input clock frequency range: 8 MHz to 40 MHz (EXTAL)
• Programmable frequency multiplication factor settings which specify VCO frequencies of
192 MHz – 600 MHz
• PLL Off mode (low-power mode)
• Register programmable output clock divider (ERFD)
• Programmable frequency modulation
— Modulation applied as a triangle waveform
— Peak-to-peak register programmable modulation depths
FMDAC_CTL[0:4]
D2AFM FMDAC
EXTAL
EPREDIV
PFD
FILTER VCO ERFD
LOC_PLL
LOC_REF
EMFD
PLL Clock
Out
Used to create the
loss of clock reset
request and decide
which PLL mode to
switch to when a
loss of clock
condition occurs