Freescale Semiconductor PXR4030, Reference Manual

Page: 563 / 1434

Enhanced Direct Memory Access Controller (eDMA)
Freescale Semiconductor 21-39
PXR40 Microcontroller Reference Manual, Rev. 1
231–239 /
0x1C [7:15]
BITER
Starting major iteration count. As the transfer control descriptor is first loaded by software, this
field must be equal to the value in the CITER field. As the major iteration count is exhausted,
the contents of this field are reloaded into the CITER field.
Note: If the channel is configured to execute a single service request, the initial values of
BITER and CITER should be 0x0001.
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0x1C [16:17]
BWC
Bandwidth control. This two-bit field provides a mechanism to effectively throttle the amount
of bus bandwidth consumed by the eDMA. In general, as the eDMA processes the inner minor
loop, it continuously generates read/write sequences until the minor count is exhausted. This
field forces the eDMA to stall after the completion of each read/write access to control the bus
request bandwidth seen by the system bus crossbar switch (XBAR).
00 No DMA engine stalls
01 Reserved
10 DMA engine stalls for 4 cycles after each r/w
11 DMA engine stalls for 8 cycles after each r/w
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0x1C [18:23]
MAJOR.LINKCH
Link channel number.
If channel-to-channel linking on major loop complete is disabled
(EDMA_x_TCD.MAJOR.E_LINK = 0) then,
• No channel-to-channel linking (or chaining) is performed after the outer major loop counter
is exhausted.
Otherwise
• After the major loop counter is exhausted, the DMA engine initiates a channel service
request at the channel defined by MAJOR.LINKCH[0:5] by setting that channel’s
EDMA_x_TCD.START bit.
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0x1C [24]
DONE
Channel done. This flag indicates the eDMA has completed the outer major loop. It is set by
the DMA engine as the CITER count reaches zero; it is cleared by software or hardware when
the channel is activated (when the DMA engine has begun processing the channel, not when
the first data transfer occurs).
Note: This bit must be cleared to write the MAJOR.E_LINK or E_SG bits.
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0x1C [25]
ACTIVE
Channel active. This flag signals the channel is currently in execution. It is set when channel
service begins, and is cleared by the DMA engine as the inner minor loop completes or if any
error condition is detected.
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0x1C [26]
MAJOR.E_LINK
Enable channel-to-channel linking on major loop completion. As the channel completes the
outer major loop, this flag enables the linking to another channel, defined by
MAJOR.LINKCH[0:5]. The link target channel initiates a channel service request via an
internal mechanism that sets the EDMA_x_TCD.START bit of the specified channel.
Note: To support the dynamic linking coherency model, this field is forced to zero when
written to while the EDMA_x_TCD.DONE bit is set.
0 The channel-to-channel linking is disabled.
1 The channel-to-channel linking is enabled.
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0x1C [27]
E_SG
Enable scatter-gather processing. As the channel completes the outer major loop, this flag
enables scatter-gather processing in the current channel. If enabled, the DMA engine uses
DLAST_SGA as a memory pointer to a 0-modulo-32 address containing a 32-byte data
structure which is loaded as the transfer control descriptor into the local memory.
Note: To support the dynamic scatter-gather coherency model, this field is forced to zero
when written to while the EDMA_x_TCD.DONE bit is set.
0 The current channel’s TCD is normal format.
1 The current channel’s TCD specifies a scatter gather format. The DLAST_SGA field
provides a memory pointer to the next TCD to be loaded into this channel after the outer
major loop completes its execution.
Table 21-21. TCDn Field Descriptions (continued)
Field Description