Freescale Semiconductor PXR4030, Reference Manual

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PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 13-1
Chapter 13
Core (e200z7) Overview
13.1 Overview
The PXR40 is a dual-issue, 32-bit PowerPC Book E compliant design with 64-bit general purpose registers
(GPRs). PowerPC Book E floating-point instructions are not supported in hardware, but are trapped and
may be emulated by software.
An Embedded Floating-point APU is provided to support real-time single-precision embedded numerics
operations using the general-purpose registers.
A second generation Signal Processing Extension APU is provided to support real-time SIMD fixed point
and single-precision, embedded numerics operations using the general-purpose registers. All arithmetic
instructions that execute in the core operate on data in the general purpose registers (GPRs). The GPRs are
64-bits in order to support vector instructions defined by the SPE2 APU. These instructions operate on
8-bit, 16-bit or 32-bit data types, and deliver vector and scalar results.
In addition to the base PowerPC Book E instruction set support, the PXR40 core also implements the VLE
(variable-length encoding) technology, providing improved code density. The VLE technology is further
documented in “PowerPC VLE Definition, Version 1.03", a separate document.
The PXR40 processor integrates a pair of integer execution units, a branch control unit, instruction fetch
unit and load/store unit, and a multi-ported register file capable of sustaining six read and three write
operations per clock. Most integer instructions execute in a single clock cycle. Branch target prefetching
is performed by the branch unit to allow single-cycle branches in many cases.
The PXR40 contains a 16Kbyte Instruction Cache, a 16Kbyte Data Cache, as well as a Memory
Management Unit. A Nexus Class 3+ module is also integrated.
13.2 Register Model
The figures below show the complete PXR40 register set for Supervisor and User Modes. The number to
the right of the special-purpose registers (SPRs) is the decimal number used in the instruction syntax to
access the register (for example, the integer exception register (XER) is SPR 1).