Freescale Semiconductor PXR4030, Reference Manual

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External Bus Interface (EBI)
30-54 Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
— rationale: these functions can be replicated by Memory Management Unit (MMU) in e200z
core
• Removed support for 8-bit ports
— rationale: reduces complexity and not required
• Removed boot chip-select operation
— rationale: on-chip Boot Assist Module (BAM) handles boot (and configuration of EBI
registers)
• Open drain mode and pullup resistors no longer required for multi-master systems, extra cycle
needed to switch between masters
— rationale: saves customer hassle for multi-master system setup, at negligible performance cost
• Address decoding for external master accesses uses 4-bit code to determine internal slave instead
of straight address decode
— rationale: needed for compatibility with internal bridge address decoding and memory map
• Removed support for 3-master systems
— rationale: very difficult to manage with internal bridge address decoding method and keep
memory maps unique; not an essential feature to justify complexity of supporting
• Removed LBDIP Base Register bit, now late D_BDIP assertion is default behavior
— rationale: unaware of any memories that require D_BDIP to assert earlier than LBDIP timing,
so reduce number of CS control bits and complexity
• Modified arbitration protocol to require extra cycles when switching between masters
— rationale: could not use exact Oak protocol and make timing for full-speed operation; adding
dead cycles to protocol allows bus to run full-speed in external master mode and makes this
feature not limit overall EBI frequency
• Added support for 32-bit coherent read & write non-chip-select accesses in 16-bit data bus mode
— rationale: some internal registers must be accessed all 32 bits at once to function as expected
• Added misaligned access support
— rationale: some eSys cores require use of misaligned accesses for optimum performance
• Added calibration access support
— rationale: support related device logic added to multiple eSys devices’s, requested customer
feature
• Added support for larger external address bus (up to 29 bits)
— rationale: support larger external memory sizes
• Added support for address/data multiplexing
— rationale: new feature to reduce minimum pin count
• Added support for using either half of data bus for 16-bit port transfers
— rationale: helps A/D muxed usability, while maintaining backwards compatibility