Freescale Semiconductor PXR4030, Reference Manual

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Enhanced Queued Analog-to-Digital Converter (EQADC)
27-76 Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
priority CFIFO is always served first. A TRIGGERED, not-underflowing CFIFO will start the transfer of
its commands when:
• its commands are bound for an internal CBuffer that is not full, and it is the highest priority
triggered CFIFO sending commands to that CBuffer.
A triggered CFIFO with commands bound for a certain CBuffer consecutively transfers its commands to
it until:
• an asserted End Of Queue bit is reached, or;
• an asserted Pause bit is encountered and the CFIFO is configured for edge trigger mode, or;
• CFIFO is configured for level trigger mode and a closed gate is detected, or;
• in case its commands are bound for an internal CBuffer, a higher priority CFIFO that uses the same
internal CBuffer is triggered, or;
The prioritization logic of the EQADC, depicted in Figure 27-54 , is composed of two independent
sub-blocks: one prioritizing CFIFOs with commands bound for CBuffer0 and another prioritizing CFIFOs
with commands for CBuffer1. As these sub-blocks are independent, simultaneous writes to CBuffer0 and
CBuffer1. The hardware identifies the destination of a command by decoding the BN bit in the command
message - see
Section 27.7.2.2, Message Format in EQADC , for details.
NOTE
Triggered but empty CFIFOs, underflowing CFIFOs, are not considered for
prioritization. No data from these CFIFOs will be sent to the CBuffers and
nor will they stop lower priority CFIFOs from transferring commands.
Whenever CBuffer0 is able to receive new entries, the prioritization sub-block selects the highest-priority
triggered CFIFO with a command bound for CBuffer0, and writes its command into the buffer. In case
CBuffer0 is able to receive new entries but there are no triggered CFIFOs with commands bound for it,
nothing is written to the buffer. The sub-block prioritizing CBuffer1 usage behaves in the same way.