Freescale Semiconductor PXR4030, Reference Manual

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Core (e200z7) Overview
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 13-37
13.9.14 Data TLB Error Interrupt (IVOR13)
A Data TLB Error interrupt occurs when no higher priority exception exists and a Data TLB Error
exception exists due to a data translation lookup miss in the TLB.
Table below lists register settings when a DTLB interrupt is taken.
13.9.15 Instruction TLB Error Interrupt (IVOR14)
A Instruction TLB Error interrupt occurs when no higher priority exception exists and an Instruction TLB
Error exception exists due to an instruction translation lookup miss in the TLB.
Exception extensions implemented in the PXR40 for PowerPC VLE involve extending the definition of
the Instruction TLB Error Interrupt to include updating the ESR.
Table 13-29 below lists register settings when an ITLB interrupt is taken.
DEAR Unchanged
Vector IVPR
0:15
|| IVOR12
16:27
|| 4b0000
1
DE is cleared when the Debug APU is disabled. Clearing of DE is optionally supported by control in HID0 when the
Debug APU is enabled.
Table 13-28. Data TLB Error Interrupt—Register Settings
Register Setting Description
SRR0 Set to the effective address of the excepting load/store instruction.
SRR1 Set to the contents of the MSR at the time of the interrupt
MSR UCLE 0
SPE
0
WE 0
CE —
EE 0
PR 0
FP 0
ME —
FE0 0
DE —
FE1 0
IS 0
DS 0
PMM 0
RI
—
ESR [ST], [SPE], [VLEMI], All other bits cleared.
MCSR Unchanged
DEAR Set to the effective address of a byte of the load or store whose access caused the violation.
Vector IVPR
0:15
|| IVOR13
16:27
|| 4b0000
Table 13-29. Instruction TLB Error Interrupt—Register Settings
Register Setting Description
SRR0 Set to the effective address of the excepting instruction.
SRR1 Set to the contents of the MSR at the time of the interrupt
Table 13-27. Watchdog Timer Interrupt—Register Settings