Freescale Semiconductor PXR4030, Reference Manual

Page: 349 / 1434

General-Purpose Static RAM (SRAM)
Freescale Semiconductor 11-3
PXR40 Microcontroller Reference Manual, Rev. 1
11.6.1 Access Timing
The system bus is a two-stage pipelined bus, which makes the timing of any access dependent on the access
during the previous clock.
Table 11-3 lists the various combinations of read and write operations to SRAM
and the number of wait states used for the each operation. The table columns contain the following
information:
Current operation Lists the type of SRAM operation executing currently
Previous operation Lists the valid types of SRAM operations that can precede the current SRAM
operation (valid operation during the preceding clock)
Wait states Lists the number of wait states (bus clocks) the operation requires which depends
on the combination of the current and previous operation
Table 11-3. Number of Wait States Required for SRAM Operations
Current Operation Previous Operation Number of Wait States Required
Read Operation
Read
Idle
1 Pipelined read
Burst read
64-bit write 2
8-, 16-, or 32-bit write
0
(read from the same address)
1
(read from a different address)
Pipelined read Read 0
Burst read
Idle
1,0,0,0 Pipelined read
Burst read
64-bit write 2,0,0,0
8-, 16-, or 32-bit write
0,0,0,0
(read from the same address)
1,0,0,0
(read from a different address)