Freescale Semiconductor PXR4030, Reference Manual

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FlexRay Communication Controller (FLEXRAY)
22-106 Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
Figure 22-127. Receive Message Buffer Access Regions
The trigger bits MBCCSRn[EDT] and MBCCSRn[LCKT] and the interrupt enable bit MBCCSRn[MBIE]
are not under access control and can be accessed from the application at any time. The status bits
MBCCSRn[EDS] and MBCCSRn[LCKS] are not under access control and can be accessed from the
controller at any time.
The interrupt flag MBCCSRn[MBIF] is not under access control and can be accessed from the application
and the controller at any time. controller set access has higher priority.
The controller restricts its access to the regions depending on the current state of the message buffer. The
application must adhere to these restrictions in order to ensure data consistency. The receive message
buffer states are given in
Figure 22-128 . A description of the message buffer states is given in Table 22-96 ,
which also provides the access scheme for the access regions.
The status bits MBCCSRn[EDS] and MBCCSRn[LCKS] provide the application with the required status
information. The internal status information is not visible to the application.
Table 22-100. Receive Message Buffer Access Region Description
Region
Access from
Region used for
Application Module
CFG read/write - Message Buffer Configuration, Message Data and Status Access
MSG read/write - Message Data, Header, and Status Access
RX - write-only Message Reception and Status Update
SR - read-only Message Buffer Search Data
Message Buffer Data Field: DATA[0-N]
Message Buffer Header Field: Frame Header
MBCCSRn[DVAL/DUP]
Message Buffer Header Field: Slot Status
Message Buffer Header Field: Data Field Offset
MBCCFRn[CHA/CHB/CCF*]
MBFIDRn[FID]
MBIDXRn[MBIDX]
MBCCSRn[MTD]
RX
SR
CFG
MSG