Freescale Semiconductor PXR4030, Reference Manual

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Interrupts and Interrupt Controller (INTC)
Freescale Semiconductor 10-17
PXR40 Microcontroller Reference Manual, Rev. 1
0x0530 83 ETPU_CISR_A[CIS15] eTPU engine A channel 15 interrupt status
0x0540 84 ETPU_CISR_A[CIS16] eTPU engine A channel 16 interrupt status
0x0550 85 ETPU_CISR_A[CIS17] eTPU engine A channel 17 interrupt status
0x0560 86 ETPU_CISR_A[CIS18] eTPU engine A channel 18 interrupt status
0x0570 87 ETPU_CISR_A[CIS19] eTPU engine A channel 19 interrupt status
0x0580 88 ETPU_CISR_A[CIS20] eTPU engine A channel 20 interrupt status
0x0590 89 ETPU_CISR_A[CIS21] eTPU engine A channel 21 interrupt status
0x05A0 90 ETPU_CISR_A[CIS22] eTPU engine A channel 22 interrupt status
0x05B0 91 ETPU_CISR_A[CIS23] eTPU engine A channel 23 interrupt status
0x05C0 92 ETPU_CISR_A[CIS24] eTPU engine A channel 24 interrupt status
0x05D0 93 ETPU_CISR_A[CIS25] eTPU engine A channel 25 interrupt status
0x05E0 94 ETPU_CISR_A[CIS26] eTPU engine A channel 26 interrupt status
0x05F0 95 ETPU_CISR_A[CIS27] eTPU engine A channel 27 interrupt status
0x0600 96 ETPU_CISR_A[CIS28] eTPU engine A channel 28 interrupt status
0x0610 97 ETPU_CISR_A[CIS29] eTPU engine A channel 29 interrupt status
0x0620 98 ETPU_CISR_A[CIS30] eTPU engine A channel 30 interrupt status
0x0630 99 ETPU_CISR_A[CIS31] eTPU engine A channel 31 interrupt status
eQADC A
0x0640 100
EQADC_FISRx[TORF]
EQADC_FISRx[RFOF]
EQADC_FISRx[CFUF]
eQADC A combined overrun interrupt request s from all of the
FIFOs:
• Trigger overrun,
• Receive FIFO overflow,
• Command FIFO underflow
0x0650 101 EQADC_FISR0[NCF] eQADC A command FIFO 0 non-coherency flag
0x0660 102 EQADC_FISR0[PF] eQADC A command FIFO 0 pause flag
0x0670 103 EQADC_FISR0[EOQF] eQADC A command FIFO 0 command queue end-of-queue flag
0x0680 104 EQADC_FISR0[CFFF] eQADC A command FIFO 0 fill flag
0x0690 105 EQADC_FISR0[RFDF] eQADC A receive FIFO 0 drain flag
0x06A0 106 EQADC_FISR1[NCF] eQADC A command FIFO 1 non-coherency flag
0x06B0 107 EQADC_FISR1[PF] eQADC A command FIFO 1 pause flag
0x06C0 108 EQADC_FISR1[EOQF] eQADC A command FIFO 1 command queue end-of-queue flag
0x06D0 109 EQADC_FISR1[CFFF] eQADC A command FIFO 1 fill flag
0x06E0 110 EQADC_FISR1[RFDF] eQADC A receive FIFO 1 drain flag
Table 10-8. Interrupt Request Sources (continued)
Hardware
Vector Mode
Offset
Vector
Number
1
Source
2
Description