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Freescale Semiconductor PXR4030, Reference Manual

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Freescale Semiconductor PXR4030 Reference Manual Download Page 434

AMBA Crossbar Switch (XBAR)

14-2

Freescale Semiconductor

PXR40 Microcontroller Reference Manual, Rev. 1

14.1.2

Block Diagram

Figure 14-1

 shows a block diagram of the crossbar switch. 

Figure 14-1. XBAR Block Diagram

Table 14-1

 gives the crossbar switch port for each master and slave, and the assigned and fixed ID number 

for each master. The following table shows the master ID numbers as they relate to the master port 
numbers:

14.1.3

Features

•

Multiple master and slave ports with programmable priorities and attributes.

Table 14-1. XBAR Switch Ports

Module

Port

Master ID

Type

Number

e200z7 core0 — CPU instruction

Master 0

0

e200z7 core0 — Data

Master 1

0

Nexus 3

8

eDMA_A

Master 4

4

eDMA_B

Master 5

5

FlexRay

Master 6

6

Reserved

1

1

This port is not usable by customers, but exists in the device. Therefore, the priority must be set 
to a unique value in the Master Priority Registers.

Master 7

3

On-chip Flash (accessed by core 0 only)

Slave 0

—

EBI (development bus)

Slave 1

—

On-chip SRAM

Slave 2

—

Peripheral bridge A (PBRIDGE_A)

Slave 6

—

Peripheral bridge B (PBRIDGE_B)

Slave 7

—

Master

Crossbar Switch

Slave

Master modules

Slave modules

Master

Master

Slave

Slave

. . . .

. . . .

Summary of Contents for PXR4030

Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...

Page 2: ...ity arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters...

Page 3: ...unication interface module UART 1 13 1 2 15 Controller area network CAN module 1 13 1 2 16 Enhanced direct memory access controller eDMA2 1 14 1 2 17 Crossbar switch XBAR 1 15 1 2 18 Power management...

Page 4: ...4 9 4 7 2 Reset Configuration Timing 4 11 4 7 3 Reset Weak Pull Up Down Configuration 4 11 Chapter 5 Power Management Controller PMC 5 1 Introduction 5 1 5 1 1 Features 5 1 5 1 1 1 Analog PMC_SMPS fe...

Page 5: ...3 2 Loss of Clock Detection 6 16 6 4 3 3 PLL Normal Mode Without FM 6 17 6 4 3 4 PLL Normal Mode With Frequency Modulation 6 19 6 5 Resets 6 22 6 5 1 Clock Mode Selection 6 22 6 5 1 1 Power On Reset...

Page 6: ...Register High SIU_CBRH 7 68 7 3 1 26 Compare B Register Low SIU_CBRL 7 69 7 3 1 27 System Clock Register SIU_SYSDIV 7 69 7 3 1 28 Halt Register SIU_HLT 7 70 7 3 1 29 Halt Acknowledge Register SIU_HLTA...

Page 7: ..._MCR 10 9 10 3 1 2 INTC Current Priority Register INTC_CPR 10 10 10 3 1 3 INTC Interrupt Acknowledge Register INTC_IACKR 10 10 10 3 1 4 INTC End of Interrupt Register INTC_EOIR 10 11 10 3 1 5 INTC Sof...

Page 8: ...12 4 12 2 2 Register Descriptions 12 7 12 2 2 1 Module Configuration Register FLASH_x_MCR 12 8 12 2 2 2 Low Mid Address Space Block Locking Register FLASH_x_LMLR 12 12 12 2 2 3 High Address Space Bloc...

Page 9: ...s 13 29 13 9 3 Data Storage Interrupt IVOR2 13 30 13 9 4 Instruction Storage Interrupt IVOR3 13 31 13 9 5 External Input Interrupt IVOR4 13 31 13 9 6 Alignment Interrupt IVOR5 13 32 13 9 7 Program Int...

Page 10: ..._OPACR 15 7 15 4 Functional Description 15 13 15 4 1 Access Support 15 13 15 4 2 Peripheral Write Buffering 15 13 15 4 2 1 Read Cycles 15 14 15 4 2 2 Write Cycles 15 14 15 4 2 3 Buffered Write Cycles...

Page 11: ..._REDR 17 16 Chapter 18 Software Watchdog Timer SWT 18 1 Introduction 18 1 18 1 1 Overview 18 1 18 1 2 Features 18 1 18 1 3 Modes of Operation 18 1 18 2 External Signal Description 18 2 18 3 Memory Map...

Page 12: ...2 External Signal Description 21 3 21 3 Memory Map and Registers 21 4 21 3 1 Module Memory Map 21 4 21 3 2 Register Descriptions 21 13 21 3 2 1 eDMA Control Register EDMA_x_MCR 21 13 21 3 2 2 eDMA Er...

Page 13: ...2 FR_A_TX Transmit Data Channel A 22 6 22 2 1 3 FR_A_TX_EN Transmit Enable Channel A 22 7 22 2 1 4 FR_B_RX Receive Data Channel B 22 7 22 2 1 5 FR_B_TX Transmit Data Channel B 22 7 22 2 1 6 FR_B_TX_E...

Page 14: ...ounter Registers SSCR0 SSCR3 22 53 22 5 2 48 MTS A Configuration Register MTSACFR 22 54 22 5 2 49 MTS B Configuration Register MTSBCFR 22 54 22 5 2 50 Receive Shadow Buffer Index Register RSBIR 22 55...

Page 15: ...rch Error 22 122 22 6 8 Individual Message Buffer Reconfiguration 22 122 22 6 8 1 Reconfiguration Schemes 22 123 22 6 9 Receive FIFOs 22 123 22 6 9 1 Overview 22 124 22 6 9 2 FIFO Configuration 22 124...

Page 16: ...MIOS200 23 1 Introduction 23 1 23 1 1 Block Diagram 23 2 23 1 2 Features 23 3 23 1 3 Modes of Operation 23 3 23 1 4 eMIOS200 Channel Configurations 23 3 23 2 External Signal Description 23 5 23 2 1 eM...

Page 17: ..._x_ESR 24 25 24 3 4 9 Interrupt Masks 2 Register FLEXCAN_x_IMASK2 24 28 24 3 4 10 Interrupt Masks 1 Register FLEXCAN_x_IMASK1 24 28 24 3 4 11 Interrupt Flags 2 Register FLEXCAN_x_IFLAG2 24 29 24 3 4 1...

Page 18: ...I_CTAR7 25 12 25 3 2 4 DSPI Status Register DSPI_SR 25 18 25 3 2 5 DSPI DMA Interrupt Request Select and Enable Register DSPI_RSER 25 20 25 3 2 6 DSPI PUSH TX FIFO Register DSPI_PUSHR 25 22 25 3 2 7 D...

Page 19: ...or DMA Request 25 60 25 4 10 3 Transfer Complete Interrupt Request 25 61 25 4 10 4 Transmit FIFO Underflow Interrupt Request 25 61 25 4 10 5 Receive FIFO Drain Interrupt or DMA Request 25 61 25 4 10 6...

Page 20: ...r Tolerance 26 27 26 4 5 SCI Mode 26 28 26 4 5 1 SCI Mode Configuration 26 28 26 4 5 2 Transmitter 26 28 26 4 5 3 Receiver 26 32 26 4 5 4 Reception Error Reporting 26 41 26 4 5 5 Multiprocessor Commun...

Page 21: ...OR1 2 27 52 27 6 3 9 ADC Pull Up Down Control Register x ADC_PUDCRx x 0 7 27 52 27 7 Functional Description 27 53 27 7 1 Overview 27 53 27 7 2 Data Flow in EQADC 27 54 27 7 2 1 Overview and Basic Term...

Page 22: ...bug Input Data Register DECFILT_x_EDID 28 22 28 2 2 10 Decimation Filter Final Integration Value Register DECFILT_x_FINTVAL 28 23 28 2 2 11 Decimation Filter Final Integration Count Value Register DEC...

Page 23: ...MISCCMPR eTPU MISC Compare Register 29 23 29 2 5 4 ETPUSCMOFFDATAR eTPU SCM Off range Data Register 29 24 29 2 5 5 ETPUECR eTPU Engine Configuration Register 29 24 29 2 6 Time Base Registers 29 27 29...

Page 24: ...ameter Coherency Methods 29 76 29 4 2 Estimating Worst Case Latency 29 76 29 4 2 1 Introduction to Worst Case Latency 29 77 29 4 2 2 Using Worst Case Latency Estimates to Evaluate Performance 29 78 29...

Page 25: ...Stop and Module Disable Modes for Power Savings 30 20 30 4 1 14 Optional Automatic D_CLKOUT Gating 30 21 30 4 1 15 Misaligned Access Support 30 21 30 4 1 16 Compatible with MPC5xx External Bus with so...

Page 26: ...on 31 19 31 7 2 Auxiliary Output Port 31 19 31 7 2 1 Output Message Protocol 31 19 31 7 2 2 Output Messages 31 20 31 7 2 3 IEEE 1149 1 2001 JTAG TAP 31 21 31 7 2 4 Nexus Auxiliary Port Sharing 31 26 3...

Page 27: ...st Mode 31 60 31 14 8 6 Block Read Access Burst Mode 31 60 31 14 8 7 Error Handling 31 61 31 14 8 8 Read Write Access Error Message 31 61 31 14 9Examples 31 61 31 14 10 IEEE 1149 1 JTAG RD WR Sequence...

Page 28: ...2 6 32 4 1 JTAGC Reset Configuration 32 6 32 4 2 IEEE 1149 1 2001 JTAG Test Access Port 32 6 32 4 3 TAP Controller State Machine 32 6 32 4 3 1 Enabling the TAP Controller 32 9 32 4 3 2 Selecting an IE...

Page 29: ...t 33 13 33 4 4 Variable Length Encoding 33 13 33 5 Peripherals and General Application Guidelines 33 14 33 6 Performance Optimization Checklist 33 14 Chapter 34 Temperature Sensor 34 1 Overview 34 1 3...

Page 30: ...PXR40 Microcontroller Reference Manual Rev 1 Freescale Semiconductor xxx...

Page 31: ...rchitecture Organization This document includes chapters that describe The microcontroller as a whole The functionality of the individual modules on the microcontroller When the microcontroller is spe...

Page 32: ...s the multi port AXBS crossbar switch that supports simultaneous connections between the master and slave ports Chapter 15 Peripheral Bridge PBRIDGE describes the interface between the system bus and...

Page 33: ...lities for the PXR40 in compliance with the IEEE ISTO 5001 2003 standard Chapter 32 IEEE 1149 1 Test Access Port Controller JTAGC describes configuration and operation of the Joint Test Action Group J...

Page 34: ...Product briefs Each device has a product brief that provides an overview of its features This document is roughly equivalent to the overview Chapter 1 of a device s reference manual Application notes...

Page 35: ...ield concatenation operator OVERBAR An overbar indicates that a signal is active low Register Figure Conventions This document uses the following conventions for the register reset values The followin...

Page 36: ...ronyms and Abbreviated Terms Term Meaning ADC Analog to digital conversion ALU Arithmetic logic unit BDM Background debug mode BIST Built in self test BSDL Boundary scan description language CODEC Cod...

Page 37: ...PLIC Physical layer interface controller PLL Phase locked loop PIN Referring to an external pin or ball i e external signal POR Power on reset RISC Reduced instruction set computing Rx Receive SOF St...

Page 38: ...ion word of the instruction ea Effective address ea y ea x Source and destination effective addresses respectively label Assembly language program label list List of registers for MOVEM instruction ex...

Page 39: ...fter then are performed If the condition is false and the optional else clause is present the operations after else are performed If the condition is false and else is omitted the instruction performs...

Page 40: ...PXR40 Microcontroller Reference Manual Rev 1 xl Freescale Semiconductor...

Page 41: ...assic PowerPC instruction set this core also has additional instruction support for digital signal processing DSP and SIMD operations The PXR40 has two levels of memory hierarchy a 32 KB Harvard archi...

Page 42: ...fers CAN_D 64 message buffers CAN_E No SPI 4 SPI_A Yes SPI_B Yes SPI_C Yes SPI_D Yes FlexRay Yes Ethernet No System timers 4 PIT chan 4 SWT 1 Watchdog eMIOS 32 channel eTPU 64 channel eTPU_A Yes eTPU2...

Page 43: ...x CAN 3 x UART 4 x SPI 4 x Dec Fil 64 ch QUAD ADCi Communications FlexRay Controller ADC Analog to digital converter ADCi ADC interface AIPS Peripheral I O bridge AMux Analog multiplexer CAN Controlle...

Page 44: ...electively disabled by software Stop mode System clock stopped to most modules including the CPU Wake up timer used to restart the system clock after a predetermined time 1 2 Packages The PXR40 is off...

Page 45: ...on Two enhanced queued analog to digital converters eQADC Support for 64 analog channels Includes one absolute reference ADC channel Includes eight decimation filters connected to eQADC_B Four deseria...

Page 46: ...maskable interrupt completely un maskable and not guaranteed to be recoverable and critical interrupt an interrupt that can be masked and is guaranteed to be recoverable sources Routed from a single p...

Page 47: ...CC Embedded hardware program and erase algorithm Erase suspend program suspend and erase suspended program Shadow information stored in non volatile shadow block Independent program erase of the shado...

Page 48: ...e its own time base Five 24 bit wide counter buses Counter bus A can be driven by unified channel 23 Counter bus B C D and E are driven by unified channels 0 8 16 and 24 respectively Counter bus A can...

Page 49: ...wnership trace messaging OTM Program trace via branch trace messaging Watchpoint messaging via the auxiliary port SCM continuous signature check built in self test MISC multiple input signature calcul...

Page 50: ...errupt source for each channel The following features are implemented One 32 bit up counter with 8 bit prescaler Four 32 bit compare channels Independent interrupt source for each channel Counter can...

Page 51: ...or conversion results 64 input channels including 16 channels which can each be converted simultaneously by each eQADC Eight additional internal channels for measuring control and monitoring voltages...

Page 52: ...ow voltage differential signalling LVDS to improve high speed operation on data and clock signals The SPIs have multiple configurations Serial peripheral interface SPI configuration where the SPI oper...

Page 53: ...Separate transmitter and receiver CPU interrupt sources 16 bit programmable baud rate modulus counter and 16 bit fractional 2 receiver wake up methods LIN features Autonomous LIN frame handling Messa...

Page 54: ...individual masking capability Selectable backwards compatibility with previous CAN version Programmable clock source to the CAN protocol interface either bus clock or crystal oscillator Unused messag...

Page 55: ...ng mechanism for continuous transfers Peripheral paced hardware requests one per channel Support for fixed priority and round robin channel arbitration Channel completion reported via optional interru...

Page 56: ...scheduling of interrupt service requests ISRs suitable for statically scheduled hard real time systems 448 software configurable interrupt sources Can be used to break the work involved in servicing a...

Page 57: ...LL running default mode out of reset PLL normal mode Each of the three modes may be run with a crystal oscillator or an external clock reference Programmable frequency modulation 1 Modulation enabled...

Page 58: ...t and output registers for setting each GPIO and virtual GPIO pin Parallel GPIO enables access to as many as eight GPIOs in one write Internal multiplexing Allows serial and parallel chaining of SPIs...

Page 59: ...10 Mbit sec and redundant communication channels The FlexRay controller provides the following features FlexRay Communications System Protocol Specification Version 2 1 Rev A compliant protocol implem...

Page 60: ...ts without using receive message buffers Measured value indicators for the clock synchronization Internal synchronization frame ID and synchronization frame measurement tables can be copied into the F...

Page 61: ...upport is supplied for MCUs without requiring external address and data pins for internal visibility The NDI block is an integration of several individual Nexus blocks that are selected to provide the...

Page 62: ...l features are independently configurable and controllable via the IEEE 1149 1 I O port The NDI block reset is controlled with JCOMP power on reset and the TAP state machine All these sources are inde...

Page 63: ...0x0000_0000 0x003F_FFFF Reserved 0x0040_0000 0x00EF_BFFF Flash B Shadow Block 0x00EF_C000 0x00EF_FFFF Reserved 0x00F0_0000 0x00FF_BFFF Flash A Shadow Block 0x00FF_C000 0x00FF_FFFF Emulation re mappin...

Page 64: ...FF0_8000 0xFFF0_FFFF MPU 0xFFF1_0000 0xFFF1_3FFF Reserved 0xFFF1_4000 0xFFF3_7FFF SWT 0xFFF3_8000 0xFFF3_BFFF STM 0xFFF3_C000 0xFFF3_FFFF ECSM 0xFFF4_0000 0xFFF4_3FFF eDMA_A 0xFFF4_4000 0xFFF4_7FFF IN...

Page 65: ...FF eSCI_B 0xFFFB_4000 0xFFFB_7FFF eSCI_C 0xFFFB_8000 0xFFFB_BFFF Reserved 0xFFFB_C0000 0xFFFB_FFFF FlexCAN_A 0xFFFC_0000 0xFFFC_3FFF FlexCAN_B 0xFFFC_4000 0xFFFC_7FFF FlexCAN_C 0xFFFC_8000 0xFFFC_BFFF...

Page 66: ...Memory Map PXR40 Microcontroller Reference Manual Rev 1 2 4 Freescale Semiconductor...

Page 67: ...Primary Function name is retained from previous MPC5xxx designs and indicates the name used on the ball map The name GPIO is also retained for clarity The remaining function names are new and have bee...

Page 68: ...ncrease and decrease as defined in Table 3 3 Table 3 2 LVDS example PCR2351 PA Selection 1 SCKC_SCK_C_LVDSP_GPIO235 PCR2362 PA Selection 2 SINC_SCK_C_LVDSM_GPIO236 SCKC Ball function SINC Ball functio...

Page 69: ...Summary GPIO PCR 1 Signal Name2 P A G 3 Function4 Function Summary Direction Pad Type 5 Voltage 6 State during RESET7 State after RESET8 Package Location 416 eTPU_A 113 TCRCLKA_IRQ7_ GPIO113 P TCRCLK...

Page 70: ...hannel output only O A2 G GPIO119 GPIO I O 120 ETPUA6_ETPUA18_ GPIO120 P ETPUA6 eTPU A channel I O MH VDDEH1 WKPCFG WKPCFG K4 A1 ETPUA18 eTPU A channel output only O A2 G GPIO120 GPIO I O 121 ETPUA7_E...

Page 71: ...channel output only O A2 G GPIO125 GPIO I O 126 ETPUA12_PCSB1_ GPIO126 P ETPUA12 eTPU A channel I O MH VDDEH1 WKPCFG WKPCFG H2 A1 PCSB1 DSPI B peripheral chip select O A2 G GPIO126 GPIO I O 127 ETPUA1...

Page 72: ...eripheral chip select O A2 G GPIO131 GPIO I O 132 ETPUA18_PCSD3_ GPIO132 P ETPUA18 eTPU A channel I O MH VDDEH1 WKPCFG WKPCFG G4 A1 PCSD3 DSPI D peripheral chip select O A2 G GPIO132 GPIO I O 133 ETPU...

Page 73: ...interrupt request I A2 G GPIO137 GPIO I O 138 ETPUA24_IRQ12_ GPIO138 P ETPUA24 eTPU A channel I O MH VDDEH1 WKPCFG WKPCFG E2 A1 IRQ12 External interrupt request I A2 G GPIO138 GPIO I O 139 ETPUA25_IRQ...

Page 74: ...ipheral chip select O A2 G GPIO143 GPIO I O 144 ETPUA30_PCSC3_ GPIO144 P ETPUA30 eTPU A channel I O MH VDDEH1 WKPCFG WKPCFG C1 A1 PCSC3 DSPI C peripheral chip select O A2 G GPIO144 GPIO I O 145 ETPUA3...

Page 75: ...hannel output only O A2 G GPIO149 GPIO I O 150 ETPUB3_ETPUB19_ GPIO150 P ETPUB3 eTPU B channel I O MH VDDEH6 WKPCFG WKPCFG R23 A1 ETPUB19 eTPU B channel output only O A2 G GPIO150 GPIO I O 151 ETPUB4_...

Page 76: ...annel output only O A2 G GPIO155 GPIO I O 156 ETPUB9_ETPUB25_ GPIO156 P ETPUB9 eTPU B channel I O MH VDDEH6 WKPCFG WKPCFG P25 A1 ETPUB25 eTPU B channel output only O A2 G GPIO156 GPIO I O 157 ETPUB10_...

Page 77: ...channel output only O A2 G GPIO161 GPIO I O 162 ETPUB15_ETPUB31_ GPIO162 P ETPUB15 eTPU B channel I O MH VDDEH6 WKPCFG WKPCFG M24 A1 ETPUB31 eTPU B channel output only O A2 G GPIO162 GPIO I O 163 ETP...

Page 78: ...IO167 P ETPUB20 eTPU B channel I O MH VDDEH6 WKPCFG WKPCFG V26 A1 A2 G GPIO167 GPIO I O 168 ETPUB21_ GPIO168 P ETPUB21 eTPU B channel I O MH VDDEH6 WKPCFG WKPCFG V25 A1 A2 G GPIO168 GPIO I O 169 ETPUB...

Page 79: ...WKPCFG WKPCFG V23 A1 A2 G GPIO173 GPIO I O 174 ETPUB27_ GPIO174 P ETPUB27 eTPU B channel I O MH VDDEH6 WKPCFG WKPCFG Y25 A1 A2 G GPIO174 GPIO I O 175 ETPUB28_ GPIO175 P ETPUB28 eTPU B channel I O MH...

Page 80: ...FlexRay 440 TCRCLKC_ GPIO4409 P MH VDDEH7 Up Up B26 A1 A2 G GPIO440 GPIO I O 441 ETPUC0_ GPIO4419 P MH VDDEH7 WKPCFG WKPCFG C25 A1 A2 G GPIO441 GPIO I O 442 ETPUC1_ GPIO4429 P MH VDDEH7 WKPCFG WKPCFG...

Page 81: ...CFG WKPCFG E25 A1 A2 G GPIO446 GPIO I O 447 ETPUC6_ GPIO4479 P I O MH VDDEH7 WKPCFG WKPCFG E26 A1 A2 G GPIO447 GPIO I O 448 ETPUC7_ GPIO4489 P I O MH VDDEH7 WKPCFG WKPCFG F23 A1 A2 G GPIO448 GPIO I O...

Page 82: ...interrupt request I A2 G GPIO452 GPIO I O 453 ETPUC12_IRQ3_ GPIO4539 P MH VDDEH7 WKPCFG WKPCFG G24 A1 IRQ3 External interrupt request I A2 G GPIO453 GPIO I O 454 ETPUC13_3_IRQ4_ GPIO4549 P MH VDDEH7 W...

Page 83: ...ive I A2 G GPIO458 GPIO I O 459 ETPUC18_FR_A_TX_EN_ GPIO4599 P MH VDDEH7 WKPCFG WKPCFG H26 A1 FR_A_TX_EN FlexRay A transfer enable O A2 G GPIO459 GPIO I O 460 ETPUC19_TXDA_ GPIO4609 P MH VDDEH7 WKPCFG...

Page 84: ...dress 0 O A3 MAB0 ADC B Mux Address 0 O G GPIO464 GPIO I O 465 ETPUC24_PCSD4_ GPIO4659 P MH VDDEH7 WKPCFG WKPCFG K24 A1 PCSD4 DSPI D peripheral chip select O A2 MAA1 ADC A Mux Address 1 O A4 MAB1 ADC...

Page 85: ...PCSD0 DSPI D peripheral chip select I O A2 G GPIO469 GPIO I O 470 ETPUC29_SCKD_ GPIO4709 P MH VDDEH7 WKPCFG WKPCFG L25 A1 SCKD DSPI D clock I O A2 G GPIO470 GPIO I O 471 ETPUC30_SOUTD_ GPIO4719 P MH...

Page 86: ...PUA2 eTPU A channel O A2 G GPIO181 GPIO I O 182 EMIOS3_ETPUA3_ GPIO182 P EMIOS3 eMIOS channel I O MH VDDEH4 WKPCFG WKPCFG AE11 A1 ETPUA3 eTPU A channel O A2 G GPIO182 GPIO I O 183 EMIOS4_ETPUA4_ GPIO1...

Page 87: ...TPUA8 eTPU A channel O A2 G GPIO187 GPIO I O 188 EMIOS9_ETPUA9_ GPIO188 P EMIOS9 eMIOS channel I O MH VDDEH4 WKPCFG WKPCFG AD13 A1 ETPUA9 eTPU A channel O A2 G GPIO188 GPIO I O 189 EMIOS10_SCKD_ GPIO1...

Page 88: ...G GPIO193 GPIO I O 194 EMIOS15_IRQ1_ GPIO194 P EMIOS15 eMIOS channel O MH VDDEH4 WKPCFG WKPCFG AD14 A1 IRQ1 External interrupt request I A2 CNRXD FlexCAN D receive I G GPIO194 GPIO I O 195 EMIOS16_ETP...

Page 89: ...WKPCFG WKPCFG AF16 A1 ETPUB4 eTPU B channel O A2 G GPIO199 GPIO I O 200 EMIOS21_ETPUB5_ GPIO200 P EMIOS21 eMIOS channel I O MH VDDEH4 WKPCFG WKPCFG AE16 A1 ETPUB5 eTPU B channel O A2 G GPIO200 GPIO I...

Page 90: ...ipheral chip select O A2 G GPIO432 GPIO I O 433 EMIOS27_PCSB3_ GPIO433 P EMIOS27 eMIOS channel I O MH VDDEH4 WKPCFG WKPCFG AC17 A1 PCSB3 DSPI B peripheral chip select O A2 G GPIO433 GPIO I O 434 EMIOS...

Page 91: ...I AE up down VDDA_A1 ANA2 ANA2 C5 ANA3 P ANA310 eQADC A analog input I AE up down VDDA_A1 ANA3 ANA3 D6 ANA4 P ANA410 eQADC A analog input I AE up down VDDA_A1 ANA4 ANA4 A5 ANA5 P ANA510 eQADC A analog...

Page 92: ...1 ANA23 ANA23 C12 AN24 P AN24 eQADC A and B shared analog input I AE VDDA_A0 AN24 AN24 B12 AN25 P AN25 eQADC A and B shared analog input I AE VDDA_A0 AN25 AN25 D13 AN26 P AN26 eQADC A and B shared ana...

Page 93: ...4 C19 ANB5 P ANB5 eQADC B analog input I AE up down VDDA_B0 ANB5 ANB5 C20 ANB6 P ANB6 eQADC B analog input I AE up down VDDA_B0 ANB6 ANB6 B19 ANB7 P ANB7 eQADC B analog input I AE up down VDDA_B0 ANB7...

Page 94: ...age reference low I VSSINT VRL_B VRL_B VRL_B A18 REFBYPCB P REFBYPCB ADC B Reference bypass capacitor I AE VDDA_B0 REFBYPCB REFBYPCB B18 REFBYPCA P REFBYPCA ADC A Reference bypass capacitor I AE VDDA_...

Page 95: ...ev 1 of the device AF3 A1 A2 G GPIO250 GPIO I O 251 FR_B_TX_ GPIO251 P FR_B_TX FlexRay B transfer O FS VDDE2 Up for Rev 1 of the device Up for Rev 1 of the device AD5 A1 A2 G GPIO251 GPIO I O 252 FR_B...

Page 96: ...p select O A2 G GPIO85 GPIO I O 86 CNRXB_PCSC4_ GPIO86 P CNRXB FlexCAN B receive I MH VDDEH4 Up Up AC19 A1 PCSC4 DSPI C peripheral chip select O A2 G GPIO86 GPIO I O 87 CNTXC_PCSD3_ GPIO87 P CNTXC Fle...

Page 97: ...O89 GPIO I O 90 RXDA _ GPIO90 P RXDA eSCI A receive I MH VDDEH1 Up Up M3 A1 A2 G GPIO90 GPIO I 91 TXDB_PCSD1_ GPIO91 P TXDB eSCI B transmit O MH VDDEH1 Up Up P1 A1 PCSD1 DSPI D peripheral chip select...

Page 98: ...3 GPIO I O 94 SINA_PCSC2_ GPIO94 P SINA DSPI A data input I MH VDDEH3 Up Up AF7 A1 PCSC2 DSPI C peripheral chip select O A2 G GPIO94 GPIO I O 95 SOUTA_PCSC5_ GPIO95 P SOUTA DSPI A data output O MH VDD...

Page 99: ...p AE7 A1 A2 G GPIO99 GPIO I O 100 PCSA4_ GPIO100 P PCSA4 DSPI A peripheral chip select O MH VDDEH3 Up Up AE5 A1 A2 G GPIO100 GPIO I O 101 PCSA5_ETRIG1_ GPIO101 P PCSA5 DSPI A peripheral chip select O...

Page 100: ...06 PCSB1_PCSD0_ GPIO106 P PCSB1 DSPI B peripheral chip select O MH VDDEH3 Up Up AC9 A1 PCSD0 DSPI D peripheral chip select I O A2 G GPIO106 GPIO I O 107 PCSB2_SOUTC_ GPIO107 P PCSB2 DSPI B peripheral...

Page 101: ...4 Up Up AD21 A1 SCK_C_LVDSP LVDS downstream signal positive output clock O A2 G GPIO235 GPIO I O 236 SINC_SCK_C_LVDSM_ GPIO236 P SINC DSPI C data input I MH LVDS VDDEH4 Up Up AE22 A1 SCK_C_LVDSM LVDS...

Page 102: ...PCSC2 DSPI C peripheral chip select O MH VDDEH5 Up Up AE23 A1 A2 G GPIO240 GPIO I O 241 PCSC3_GPIO241 P PCSC3 DSPI C peripheral chip select O MH VDDEH5 Up Up AD23 A1 A2 G GPIO241 GPIO I O 242 PCSC4_GP...

Page 103: ...4_ GPIO208 P PLLCFG0 FMPLL mode configuration input I MH VDDEH1 PLLCFG Up Input Up R3 A1 IRQ4 External interrupt request I A2 G GPIO208 GPIO I O 209 PLLCFG1_IRQ5_ GPIO209 P PLLCFG1 FMPLL mode configur...

Page 104: ...2 of the device 13 MDO015 Nexus message data out O F VDDE2 O Low MDO0 Low U3 A1 A2 G GPIO220 GPIO I O 221 MDO1_GPIO221 GPIO function on this pin is only available on Rev 2 of the device 13 MDO115 Nex...

Page 105: ...VDDE2 O Low Down W1 A1 A2 G GPIO77 GPIO I O 78 MDO7_GPIO78 GPIO function on this pin is only available on Rev 2 of the device 13 MDO715 Nexus message data out O F VDDE2 O Low Down W2 A1 A2 G GPIO78 GP...

Page 106: ...s message data out O F VDDE2 O Low Down AA1 A1 A2 G GPIO231 GPIO I O 232 MDO13_GPIO232 13 MDO1315 Nexus message data out O F VDDE2 O Low Down AA2 A1 A2 G GPIO232 GPIO I O 233 MDO14_GPIO233 13 MDO1415...

Page 107: ...L REGCTL Y26 VSSFL VSSFL Tie to VSS I VSS VDDREG VSSFL VSSFL AB25 VDDREG VDDREG Source voltage for on chip regulators and Low voltage detect circuits I VDDINT VDDREG VDDREG VDDREG AA25 1 The GPIO numb...

Page 108: ...al name to the left or right of the slash indicates the pin is enabled 8 The Function After Reset of a GPI function is general purpose input A dash on the left side of the slash denotes that both the...

Page 109: ...8 ETPUA15_PCSB5_GPIO129 ETPUA16_PCSD1_GPIO130 Input output channel pin for the eTPU A module The first alternate function is a peripheral chip select for the DSPI D module ETPUA17_PCSD2_GPIO131 ETPUA1...

Page 110: ...function assigned to it The primary function is reserved for eTPU_C for compatibility with future devices ETPUC6_GPIO447 This pin does not have a primary function assigned to it The primary function i...

Page 111: ...93 EMIOS 14 _IRQ 0 _GPIO 193 is an output channel pin for the eMIOS module The alternate function is an external interrupt request input EMIOS15_IRQ1_GPIO194 EMIOS 15 _IRQ 1 _GPIO 194 is an output cha...

Page 112: ...acitor between the REFBYPCA pin and VRLA The value of this capacitor must be 100nF This bypass capacitor is used to provide a stable reference voltage for the ADC VDDA_A0 VDDAn is the analog supply in...

Page 113: ...e receive pin for the eSCI A module CNTXB_PCSC3_GPIO85 Transmit pin for the FlexCAN B module Alternate function is a peripheral chip select output for the DSPI C module CNRXB_PCSC4_GPIO86 Receive pin...

Page 114: ...CI B module 1 This signal name includes eTPU_C functionality that this device does not have This is for forward compatibility with devices that have an eTPU_C Table 3 12 DSPI Signals Signal Name Descr...

Page 115: ...7 Data output pin for the DSPI C module The alternate function is the LVDS version of SOUTC PCSC0_SOUT_C_LVDSM_ GPIO238 Peripheral chip select for the DSPI C module The alternate function is the LVDS...

Page 116: ...Only Signal Name Description D_CS0_GPIO256 EBI chip select output signal D_CS2_D_DAT31_GPIO257 EBI chip select output signal The alternate function is data signal 31 D_CS3_D_TEA_GPIO258 EBI chip sele...

Page 117: ...set the all modules of the device MCU The RESET pin must be asserted during a power on reset RSTOUT The RSTOUT output is a push pull output that is asserted during an internal device reset The pin can...

Page 118: ...ut to the development tools In addition MDO 0 indicates the lock status of the system clock following a power on reset There is an internal pullup on MDO 0 This pin functions as GPIO when Nexus messag...

Page 119: ...internal SRAM during power down If not used tie VSTBY to VSS VSSFL VSSFL must be tied to VSS VDDREG Source voltage for on chip regulators and low voltage detect LVD circuits VDDEHn VDDEn I O supply in...

Page 120: ...Signal Descriptions 3 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...

Page 121: ...t resets internal logic and controls the assertion of the RSTOUT pin The Software External Reset only causes the RSTOUT pin to be asserted for a number of clock cycles determined by the PLL mode refer...

Page 122: ...reset vector for this device is 0xFFFF_FFFC This is a fixed location in the BAM The BAM program executes after every internal reset The BAM program determines where to branch after its execution comp...

Page 123: ...al The FMPLL Loss of Lock reset request is connected to both a reset request and a reset gating signal in the SIU The FMPLL asserts the Loss of Lock reset request until the PLL has achieved lock 4 5 R...

Page 124: ...Manual Rev 1 4 4 Freescale Semiconductor Figure 4 1 External Reset Flow Diagram Asserted F T RESET F T Asserted RESET Asserted RESET A Wait 2 Clock Cycles Set Latch Wait 8 Clock Set RGF Bit To entry p...

Page 125: ...set F T F T Clock Cycles Clock Cycles F T Latch WKPCFG Pin Latch PLLREF BOOTCFG Reset Request RSTOUT Negate Internal Resets and Wait 24001 Wait 4 Clock Cycles Wait n1 Apply WKPCFG Pin RSTOUT Assert In...

Page 126: ...MPLL Loss of Lock reset request signal The internal reset signal and RSTOUT are kept asserted until the FMPLL negates the Loss of Lock reset request signal After the Loss of Lock reset request signal...

Page 127: ...clocks which is different than the peripheral platform clocks and a time out occurs with the Enable Next Watchdog Timer EWT and Watchdog Timer Interrupt Status WIS bits set in the Timer Status Registe...

Page 128: ...r then waits 4 clock cycles before negating RSTOUT and the associated bits fields are updated in the SIU_RSR In addition the SSRS bit is set and all other reset status bits in the SIU_RSR are cleared...

Page 129: ...spectively The locations for the RCHW are given in Table 4 4 For internal boot the predefined locations are searched in the order given in the table If a valid RCHW is not found in internal boot mode...

Page 130: ...5 WTE MCU core watchdog timer enable This bit determines if the core software watchdog timer is enabled after passing control to the user application code 0 Disable core software watchdog timer 1 Enab...

Page 131: ...al Description chapter for the eTPU and eMIOS pins that are affected by WKPCFG For all reset sources except the Software External Reset the WKPCFG pin is applied at the assertion of the internal reset...

Page 132: ...onductor the eTPU and eMIOS pins caused by switching pull up down states The final value of WKPCFG is latched 4 clock cycles before the negation of RSTOUT After reset software may modify the weak pull...

Page 133: ...ge is recommended to operate and defines the VDDREG LVD level to 3V High precision Low Voltage Detector LVD monitor for PMC supply voltage VDDREG VDD core voltage supply and VDDSYN A low voltage band...

Page 134: ...llowed Monitors the following supplies core voltage pin that connects in the package to core voltage 3 3V via the VDD33 pin input to the 3 3V network 5V on VDDREG Disabling 3 3 V internal regulator Se...

Page 135: ...Name Description LDO3V 3 3V Voltage Supply LDO regulator enabled When external pin REGSEL is connected to VSS it has a weak internal resistive pull down and regulator supply voltage is 3 3V nominal th...

Page 136: ...as the internal 3 3V regulator An external ballast transistor is expected on REGCTL as described in 1 2V LDO regulator section An external decoupling capacitor is expected on VDDSYN details in the 3...

Page 137: ...at VDD33 hence it is recommended to short VDDSYN and VDD33 with low impedance short track When the internal regulator is disabled the pin has a weak 35 k pull down resistor and VDDSYN must be connect...

Page 138: ...0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5 2 Configuration and Status Register PMC_MCR Table 5 4...

Page 139: ...upply falls below the corresponding LVD threshold The low voltage interrupt is independent from low voltage reset If both interrupt and reset are enabled then reset and interrupt will be generated but...

Page 140: ...terrupt 0 Disabled Low voltage interrupt request is disabled 1 Enabled Low voltage interrupt request is enabled 14 Reserved 15 TLK Trimming lock This is a set only bit that comes out of reset negated...

Page 141: ...mV 1010 LVDA 100 mV 1001 LVDA 120 mV 1000 LVDA 140 mV 12 15 LVDREGTRIM Description This field is used to fine tune the voltage threshold of LvdReg the rising LVD used to monitor the VDDREG supply ris...

Page 142: ...VDD33 6 STEPV33 1000 VDD33 7 STEPV33 20 23 LVD33TRIM Description LVD 3 3V trimming This field is used to fine tune the rising voltage threshold of the VDDSYN supply which can be internally regulated...

Page 143: ...12 1011 VDD12OUT 4 STEPV12 1010 VDD12OUT 5 STEPV12 1001 VDD12OUT 6 STEPV12 1000 VDD12OUT 7 STEPV12 28 31 LVDCTRIM Description LVD 1 2V trimming This field is used to fine tune the rising voltage thres...

Page 144: ...to the LVFCSTBY bit 0 No occurrence 1 LVD occurrence or brownout reported by the RAM standby regulator switch 6 BGRDY Bandgap ready This read only bit gets asserted when the PMC bandgap circuit has f...

Page 145: ...read only bit is the low voltage flag associated with the supply of the I O segment that contains the reset pin It is asserted when the supply falls below the corresponding LVD threshold and can be c...

Page 146: ...ad only bit is the low voltage flag associated with the VDDSYN 3 3 V supply It is asserted when the 3 3 V supply falls below the corresponding LVD threshold and can be cleared by the CPU by writing 1...

Page 147: ...rising slope may vary 5 5 1 PMC Internal 1 2V Voltage Regulator Selection The PMC features two main regulators for core supply voltage VDD The selection is done at board level by connecting the REGSE...

Page 148: ...set and default value of the 4 bit register is 1111 corresponding to the nominal LvdReg voltage LVD scaled voltage can be measured via ADC by selecting the respective channel reported in Table 5 8 Dur...

Page 149: ...ower connection Tolerance of the 3 3V regulator reported in the PXR40 Microcontroller Data Sheet assumes appropriate decoupling capacitance on VDDSYN pin maximum current load less than or equal to IDD...

Page 150: ...bipolar selected The switched controller is a full analog asynchronous regulator with ramp compensation and equalized error integration It is used to drive an external high side n MOS driver Schottky...

Page 151: ...e tapped output The reset value of the 4 bit register is 0110 corresponding to the nominal LVD12 voltage When an internal regulator SMPS or LDO is used to generate the core voltage supply it is requir...

Page 152: ...ich is asserted whenever any of the individual interrupt request signals becomes asserted 5 5 10 PMC Power on Reset A Power on reset POR circuit monitors its supply voltage providing a logic reset in...

Page 153: ...VD rising and falling edges POR_B POR_B Asserts POR_B Negates POR_B Asserts POR_B Indeterminate Indeterminate Ramp Up Ramp Down Power Supply Specified Power Supply Range POR_B Asserts POR_B Negates PO...

Page 154: ...e to calculate the approximate target LVD or regulator value Vtarget is equal to Vtarget Vsupply Vbg Vadc During LVD measurement the continuous time monitoring is temporarily disabled as the multiplex...

Page 155: ...tart begin When the internal regulator is used to generate 1 2V core supply it is required to write 1100 to the LVDCTRIM field before clock frequency is increased 5 7 Application Information 5 7 1 Reg...

Page 156: ...nal Description BCP68T1 npn ON Semiconductor NJD2874 npn ON Semiconductor 3BCP68 npn NXP Semiconductors capacitor 6 x 4 7 F 20V Ceramic low ESR One for each VDD pin capacitor 6 x 0 1 F 20V Ceramic One...

Page 157: ...Low Vf Schottky diode SI3460f nMOS Low threshold n MOS LQH66SN2R2M03 inductor 2 2 H 3 2A muRata unshielded or shielded coil C3225X7R1E106M capacitor 2X10uF 25V TDK high capacitance ceramic SMD on VDD...

Page 158: ...Power Management Controller PMC 5 26 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...

Page 159: ...rm are register programmable through a peripheral bus interface Figure 6 1 shows the operating frequency domains of the various blocks on this device Figure 6 1 PXR40 Block Operating Frequency Domain...

Page 160: ...Section 6 4 3 3 PLL Normal Mode Without FM for details on each sub block Figure 6 2 FMPLL Block Diagram 6 1 2 Features The FMPLL has these major features refer to PXR40 Microcontroller Data Sheet for...

Page 161: ...A full swing square wave clock input for the entire system must be supplied on the EXTAL pin Refer to PXR40 Microcontroller Data Sheet for external clock input requirements This operating mode is des...

Page 162: ...r 32 R W 1 6 3 2 4 6 12 1 See specific register description Offset FMPLL_BASE_ADDR 0x0004 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0...

Page 163: ...1 or reset is asserted 0 Interrupt service not requested 1 Interrupt service requested 23 LOC Loss Of Clock Status The LOC bit is an indication of whether a loss of clock condition is present when ope...

Page 164: ...equency modulation enabled 1 PLL has not lost lock since last system reset a write to ESYNCR1 to modify the ESYNCR1 EMFD and ESYNCR1 EPREDIV bit fields or frequency modulation enabled 28 LOCK PLL Lock...

Page 165: ...PLLREF bits in the SYNSR These change the clock mode after reset has negated via software CLKCFG 2 0 map directly to MODE PLLSEL and PLLREF to control the system clock mode Note CLKCFG 0b101 or any r...

Page 166: ...quency must be within the fVCO specification see the PXR40 Microcontroller Data Sheet When the EMFD bits are changed the PLL loses lock Do not change the EMFD bits during FM operation Before changing...

Page 167: ...hanced Synthesizer Control Register 2 ESYNCR2 Table 6 6 ESYNCR2 Bit Field Descriptions Field Description 0 7 Reserved 8 LOCEN Loss of Clock Enable The LOCEN bit determines whether the loss of clock fu...

Page 168: ...fect in PLL Off mode 0 Request interrupt on loss of clock is disabled 1 Request interrupt on loss of clock 13 Reserved 14 15 ERATE1 Enhanced Modulation Rate The ERATE bits control the rate of frequenc...

Page 169: ...to the next falling edge of the current system clock These bits should be written only when the lock bit LOCK is set to avoid surpassing the allowable system operating frequency In PLL Off mode the E...

Page 170: ...CTL W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6 6 FMPLL Synthesizer FM Control Register SYNFMCR Table 6 9...

Page 171: ...eration 00100 1 01000 2 01100 3 10000 4 These values have been shown in characterization data to produce the specified FM percentage within the device specification However the user may program interm...

Page 172: ...henever PLLCFG 0 1 are changed in reset to a value other than what it was before the reset an immediate loss of lock condition is declared This only applies if the PLL was running in a locked state pr...

Page 173: ...epeated for N K counts Then if the two counters counts match the lock criteria is relaxed by one count and the system is notified that the PLL has achieved frequency lock After three successful compar...

Page 174: ...to the phase frequency detector PFD see Figure 6 2 When the reference or feedback clock frequency falls below a minimum frequency the LOC circuitry considers the clock to have failed and a loss of clo...

Page 175: ...ined in the feedback loop of the PLL so changing the ERFD bits does not affect FMPLL operation Finally the PLL can be frequency modulated to reduce electromagnetic interference often associated with c...

Page 176: ...in the loop allows the PLL to perform frequency multiplication or synthesis 6 4 3 3 5 Programming System Clock Frequency In normal PLL clock mode the default system frequency is determined by the defa...

Page 177: ...cy Follow the above procedure for step 1 In step 2 rather than set ERFD to ERFD from step 1 2 set this to a value which will produce a low system frequency close to the default system frequency e g ER...

Page 178: ...dulation The following steps illustrate proper programming of the frequency modulation mode These steps ensure proper operation of the FM configuration routine and prevent frequency overshoot from the...

Page 179: ...achieves lock write the desired ERFD value Make sure not to modify ERATE EDEPTH as they share the same register space The frequency modulation system is dependent on several factors including the acc...

Page 180: ...eset until the negation of the POR signal This prevents the PLL from attempting to lock before its supplies are within specification which can cause VCO loop gain to be lower than what the analog loop...

Page 181: ...Register SIU_RSR must be read to determine a loss of lock condition occurred In PLL Off mode the PLL cannot lock therefore a loss of lock condition cannot occur and LOLRE has no effect 6 5 3 PLL Loss...

Page 182: ...Frequency Modulated Phase Locked Loop FMPLL 6 24 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...

Page 183: ...1 Introduction This chapter describes the device system integration unit SIU that configures and initializes the following controls MCU reset configuration System reset operation Pad configuration Ext...

Page 184: ...The power on reset detection module pad interface pad ring module and peripheral I O channels shown shaded in Figure 7 1 are external to the SIU Reset RESET configuration SIU registers Reset controlle...

Page 185: ...ons Pullup and pulldown characteristics of the pin Slew rate for slow and medium pads Open drain mode for output pins Hysteresis for input pins Drive strength of bus signals for fast pads External int...

Page 186: ...s at the beginning RESET has a glitch detector logic that senses electrical fluctuations on the VDDEH input pins that drop below the switch point value for more than two clock cycles The switch point...

Page 187: ...gister The SIU also implements several parallel GPIO registers SIU_PGPDOx_x and SIU_PGPDIx_x that can be used to access up to 32 GPIO bits in a single and word sized accesses The values read written t...

Page 188: ...weak pulldown pin characteristics after a reset occurs in the eMIOS or eTPU modules The value of WKPCFG is latched at reset stored in the reset status register SIU_RSR and updated for all reset source...

Page 189: ...lect register 32 R W 0x0000_0000 7 3 1 6 7 17 SIU_BASE 0x0020 SIU_OSR Overrun status register 32 R W 0x0000_0000 7 3 1 7 7 18 SIU_BASE 0x0024 SIU_ORER Overrun request enable register 32 R W 0x0000_000...

Page 190: ...980 SIU_CCR Chip Configuration Register 32 R W 0x000X_0000 7 3 1 23 7 66 SIU_BASE 0x0984 SIU_ECCR External Clock Control Register 32 R W 0x0000_1001 7 3 1 24 7 67 SIU_BASE 0x0988 0x098C Reserved SIU_B...

Page 191: ...ETPUBA DSPIA eTPUB Select Register 32 R W 0x0000_0000 7 3 1 33 2 7 79 SIU_BASE 0x0D44 SIU_EMIOSA DSPIA eMIOS Select Register 32 R W 0x0000_0000 7 3 1 33 2 7 79 SIU_BASE 0x0D48 SIU_DSPIAHLA DSPIA SIU_D...

Page 192: ...anges The mask number is a read only field that is mask programmed with the specific mask revision level of the device The current value applies to revision 0 and is updated for each mask revision The...

Page 193: ...est is set Address SIU_BASE 0x0004 Access Read Only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R PARTNUM W PXR40 part number 0 1 0 1 0 1 1 0 0 1 1 1 0 1 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31...

Page 194: ...1 Loss of clock Loss of lock Core Watchdog or Debug Platform Watchdog Lower 2 Software external reset Lowest 3 Address SIU_BASE 0x000C Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R PORS ERS LLRS...

Page 195: ...ler was a loss of clock reset 4 WDRS Core Watchdog timer debug reset status 0 The last reset source acknowledged by the reset controller was not a watchdog timer or debug reset 1 The last reset source...

Page 196: ...by the assertion of the power on reset input to the reset controller or a write of 1 to the RGF bit Refer to Section 7 4 2 2 RESET Pin Glitch Detect for more information on glitch detection 0 No glit...

Page 197: ...note2 2 Write 1 to the SER bit to generate a software external reset A write of 0 to this bit has no effect When the reset completes the SER bit is cleared to 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1...

Page 198: ...troller The EIRE bits determine the external interrupt requests that assert the SIU interrupt request to the interrupt controller Address SIU_BASE 0x0014 Access R w1c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 1...

Page 199: ...12 SIU_DIRER Bit Field Descriptions Field Description 0 NMISEL8 Non Maskable Interrupt Critical Interrupt Selection NMI comes from external pin SIU generates two specific sources of interrupt to the...

Page 200: ...0 0 0 0 Figure 7 7 DMA Interrupt Request Select Register SIU_DIRSR Table 7 13 SIU_DIRSR Bit Field Descriptions Field Description 0 27 Reserved 28 31 DIRSn DMA interrupt request select n Selects betwe...

Page 201: ...n an overrun occurs on IRQ n Bit 31 OVF0 is the overrun flag for IRQ 0 bit 16 OVF15 is overrun flag for IRQ 15 0 No overrun occurred 1 An overrun occurred Address SIU_BASE 0x0024 Access R W 0 1 2 3 4...

Page 202: ...8 9 10 11 12 13 14 15 R IREE_ NMI8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R IREE 15 IREE 14 IREE 13 IREE 12 IREE 11 IREE...

Page 203: ...10 11 12 13 14 15 R IFEE_ NMI8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R IFEE 15 IFEE 14 IFEE 13 IFEE 12 IFEE 11 IFEE 10...

Page 204: ...e filtered values of the NMI and IRQ 0 IRQ 15 pins are captured Address SIU_BASE 0x0030 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0...

Page 205: ...28 29 30 31 R IFI15 IFI14 IFI13 IFI12 IFI11 IFI10 IFI9 IFI8 IFI7 IFI6 IFI5 IFI4 IFI3 IFI2 IFI1 IFI0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 7 13 IRQ Filtered Input Register SIU_IFIR Table 7 19...

Page 206: ...boundaries or 32 bit values aligned on 32 bit address boundaries NOTE The fields available in a SIU_PCR depend on the type of pad it controls Refer to the SIU_PCR definition All device pin names begin...

Page 207: ...put buffer for the pad 1 Enable input buffer for the pad is enabled 8 9 DSC Drive strength control Controls the pad drive strength Drive strength control pertains to pins with the fast I O pad type 00...

Page 208: ...hether the weak pullup down devices are enabled disabled for the pad Pullup down devices are enabled by default 0 Disable weak pull device for the pad 1 Enable weak pull device for the pad 15 WPS Weak...

Page 209: ...ers controlling these pins which is used to mux the input sources and allow only one active input The multiple source inputs with PCR priority is given in Table 7 21 Table 7 21 PCR priority for multip...

Page 210: ...00E2 GPIO813 MDO10 0 0 1 1 822 0x00E4 GPIO823 MDO11 0 0 1 1 83 0x00E6 GPIO83 CNTXA TXDA4 0 0 0 0 0 0 0 0 1 1 84 0x00E8 GPIO84 CNRXA RXDA4 0 0 0 0 0 0 0 0 1 1 85 0x00EA GPIO85 CNTXB PCSC3 0 0 0 0 0 0 0...

Page 211: ...0 0 0 0 0 1 1 109 0x011A GPIO109 PCSB4 SCKC4 0 0 0 0 0 0 0 0 1 1 110 0x011C GPIO110 PCSB5 PCSC04 0 0 0 0 0 0 0 0 1 1 113 0x0122 GPIO113 TCRCLKA IRQ7 0 0 0 0 0 0 0 0 1 1 114 0x0124 GPIO114 ETPUA0 ETPU...

Page 212: ...0 0 1 U 133 0x014A GPIO133 ETPUA19 PCSD4 0 0 0 0 0 0 0 0 1 U 134 0x014C GPIO134 ETPUA20 IRQ8 0 0 0 0 0 0 0 0 1 U 135 0x014E GPIO135 ETPUA21 IRQ9 0 0 0 0 0 0 0 0 1 U 136 0x0150 GPIO136 ETPUA22 IRQ10 0...

Page 213: ...0 0 1 U 156 0x0178 GPIO156 ETPUB9 ETPUB25 0 0 0 0 0 0 0 0 1 U 157 0x017A GPIO157 ETPUB10 ETPUB26 0 0 0 0 0 0 0 0 1 U 158 0x017C GPIO158 ETPUB11 ETPUB27 0 0 0 0 0 0 0 0 1 U 159 0x017E GPIO159 ETPUB12...

Page 214: ...0 0 0 0 0 0 0 1 U 180 0x01A8 GPIO180 EMIOS1 ETPUA1 0 0 0 0 0 0 0 0 1 U 181 0x01AA GPIO181 EMIOS2 ETPUA2 0 0 0 0 0 0 0 0 1 U 182 0x01AC GPIO182 EMIOS3 ETPUA3 0 0 0 0 0 0 0 0 1 U 183 0x01AE GPIO183 EMIO...

Page 215: ...5 0 0 0 0 0 0 0 0 1 U 201 0x01D2 GPIO201 EMIOS22 ETPUB6 0 0 0 0 0 0 0 0 1 U 202 0x01D4 GPIO202 EMIOS23 ETPUB7 0 0 0 0 0 0 0 0 1 U 203 0x01D6 GPIO203 EMIOS24 PCSB04 0 0 0 0 0 0 0 0 1 U 204 0x01D8 GPIO2...

Page 216: ...PIO235 SCKC SCK_C_LVDS 0 0 0 0 0 0 0 0 1 1 236 0x0218 GPIO236 SINC SCK_C_LVDS 0 0 0 0 0 0 0 0 1 1 237 0x021A GPIO237 SOUTC SOUT_C_LVDS 0 0 0 0 0 0 0 0 1 1 238 0x021C GPIO238 PCSC0 SOUT_C_LVDS 0 0 0 0...

Page 217: ..._TEA 0 0 0 0 0 0 0 0 1 1 259 0x0246 GPIO259 D_ADD12 0 0 0 0 0 0 0 1 1 260 0x0248 GPIO260 D_ADD13 0 0 0 0 0 0 0 1 1 261 0x024A GPIO261 D_ADD14 0 0 0 0 0 0 0 1 1 262 0x024C GPIO262 D_ADD15 0 0 0 0 0 0 0...

Page 218: ...1 1 280 0x0270 GPIO280 D_ADD_DAT2 0 0 0 0 0 0 0 1 1 281 0x0272 GPIO281 D_ADD_DAT3 0 0 0 0 0 0 0 1 1 282 0x0274 GPIO282 D_ADD_DAT4 0 0 0 0 0 0 0 1 1 283 0x0276 GPIO283 D_ADD_DAT5 0 0 0 0 0 0 0 1 1 284...

Page 219: ...304 D_WE3 0 0 0 0 0 0 0 1 1 305 0x02A2 GPIO305 D_ADD9 0 0 0 0 0 0 0 1 1 306 0x02A4 GPIO306 D_ADD10 0 0 0 0 0 0 0 1 1 307 0x02A6 GPIO307 D_ADD11 0 0 0 0 0 0 0 1 1 432 0x03A0 GPIO432 EMIOS26 PCSB2 0 0 0...

Page 220: ...0 0 0 0 0 0 1 U 454 0x03CC GPIO454 IRQ44 0 0 0 0 0 0 0 0 1 U 455 0x03CE GPIO455 IRQ54 0 0 0 0 0 0 0 0 1 U 456 0x03D0 GPIO456 0 0 0 0 0 0 0 1 U 457 0x03D2 GPIO457 FR_A_TX 0 0 0 0 0 0 0 0 1 U 458 0x03D...

Page 221: ...y be affected by a higher priority PCR See Table 7 21 5 When the SIU_ISEL8 register is in its default state this eTPU pin will not be enabled as an input irrespective of the SIU_PCR PA field 6 PCR231...

Page 222: ...function is assigned except you can read the value back that was just written 7 3 1 15 GPIO Pin Data Input Registers 0 255 SIU_GPDIn NOTE This register is implemented for legacy purposes and is limite...

Page 223: ...e SIU_EIISR selects the source for the external interrupt DMA inputs Address SIU_BASE 0x0800 n Read Only 0 1 2 3 4 5 6 7 R 0 0 0 0 0 0 0 PDIn W Reset 0 0 0 0 0 0 0 0 Figure 7 16 General Purpose Data I...

Page 224: ...e input for IRQ 12 00 IRQ 12 pin 01 DSPI_B 12 deserialized input 10 DSPI_C 13 deserialized input 11 DSPI_D 14 deserialized input 8 9 ESEL11 External IRQ input select 11 Specifies the input for IRQ 11...

Page 225: ...ect 4 Specifies the input for IRQ 4 00 IRQ 4 pin 01 DSPI_B 5 deserialized input 10 DSPI_C 6 deserialized input 11 DSPI_D 1 deserialized input 24 25 ESEL3 External IRQ input select 3 Specifies the inpu...

Page 226: ...d Descriptions Field Description 0 1 SINSELA DSPI A data input select Specifies the source of the DSPI A data input 00 SINA_PCSC 2 _GPIO 94 pin 01 SOUTB 10 SOUTC 11 SOUTD 2 3 SSSELA DSPI A slave selec...

Page 227: ...ct Specifies the source of the DSPI C data input 00 PCSB 3 _SINC_GPIO 108 pin 01 SOUTA 10 SOUTB 11 SOUTD 18 19 SSSELC DSPI C slave select input select Specifies the source of the DSPI C slave select i...

Page 228: ...ut can be programmed to recognize either rising or falling edges and low or high gated trigger types 26 27 SSSELD DSPI D slave select input select Specifies the source of the DSPI D slave select input...

Page 229: ...0 0 0 0 0 0 0 0 SIU_ISEL6 eTRIG_B 5 2 Address SIU_BASE 0x0918 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 cTSEL5_1 0 cTSEL4_1 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 2...

Page 230: ...1 PIT3 Trigger 0 0 1 1 0 Reserved 0 0 1 1 1 eTRIG1 pin 0 1 0 x x Reserved 0 1 1 0 0 eTPUA28 0 1 1 0 1 eTPUA29 0 1 1 1 0 eTPUA30 0 1 1 1 1 eTPUA31 1 0 0 0 0 eTPUB28 1 0 0 0 1 eTPUB29 1 0 0 1 0 eTPUB30...

Page 231: ...0 1 PIT3 Trigger 0 0 1 1 0 eTPUA7 0 0 1 1 1 eTRIG0 pin 0 1 0 x x Reserved 0 1 1 0 0 eTPUA28 0 1 1 0 1 eTPUA29 0 1 1 1 0 eTPUA30 0 1 1 1 1 eTPUA31 1 0 0 0 0 eTPUB28 1 0 0 0 1 eTPUB29 1 0 0 1 0 eTPUB30...

Page 232: ...1 PIT3 Trigger 0 0 1 1 0 eTPUA14 0 0 1 1 1 eTRIG1 pin 0 1 0 x x Reserved 0 1 1 0 0 eTPUA28 0 1 1 0 1 eTPUA29 0 1 1 1 0 eTPUA30 0 1 1 1 1 eTPUA31 1 0 0 0 0 eTPUB28 1 0 0 0 1 eTPUB29 1 0 0 1 0 eTPUB30...

Page 233: ...1 PIT3 Trigger 0 0 1 1 0 eTPUA22 0 0 1 1 1 eTRIG0 pin 0 1 0 x x Reserved 0 1 1 0 0 eTPUA28 0 1 1 0 1 eTPUA29 0 1 1 1 0 eTPUA30 0 1 1 1 1 eTPUA31 1 0 0 0 0 eTPUB28 1 0 0 0 1 eTPUB29 1 0 0 1 0 eTPUB30...

Page 234: ...1 PIT3 Trigger 0 0 1 1 0 eTPUA30 0 0 1 1 1 eTRIG1 pin 0 1 0 x x Reserved 0 1 1 0 0 eTPUA28 0 1 1 0 1 eTPUA29 0 1 1 1 0 eTPUA30 0 1 1 1 1 eTPUA31 1 0 0 0 0 eTPUB28 1 0 0 0 1 eTPUB29 1 0 0 1 0 eTPUB30...

Page 235: ...1 PIT3 Trigger 0 0 1 1 0 Reserved 0 0 1 1 1 eTRIG0 pin 0 1 0 x x Reserved 0 1 1 0 0 eTPUA28 0 1 1 0 1 eTPUA29 0 1 1 1 0 eTPUA30 0 1 1 1 1 eTPUA31 1 0 0 0 0 eTPUB28 1 0 0 0 1 eTPUB29 1 0 0 1 0 eTPUB30...

Page 236: ...1 PIT3 Trigger 0 0 1 1 0 Reserved 0 0 1 1 1 eTRIG1 pin 0 1 0 x x Reserved 0 1 1 0 0 eTPUA28 0 1 1 0 1 eTPUA29 0 1 1 1 0 eTPUA30 0 1 1 1 1 eTPUA31 1 0 0 0 0 eTPUB28 1 0 0 0 1 eTPUB29 1 0 0 1 0 eTPUB30...

Page 237: ...0 1 PIT3 Trigger 0 0 1 1 0 eTPUA7 0 0 1 1 1 eTRIG0 pin 0 1 0 x x Reserved 0 1 1 0 0 eTPUA28 0 1 1 0 1 eTPUA29 0 1 1 1 0 eTPUA30 0 1 1 1 1 eTPUA31 1 0 0 0 0 eTPUB28 1 0 0 0 1 eTPUB29 1 0 0 1 0 eTPUB30...

Page 238: ...1 PIT3 Trigger 0 0 1 1 0 eTPUA14 0 0 1 1 1 eTRIG1 pin 0 1 0 x x Reserved 0 1 1 0 0 eTPUA28 0 1 1 0 1 eTPUA29 0 1 1 1 0 eTPUA30 0 1 1 1 1 eTPUA31 1 0 0 0 0 eTPUB28 1 0 0 0 1 eTPUB29 1 0 0 1 0 eTPUB30...

Page 239: ...1 PIT3 Trigger 0 0 1 1 0 eTPUA22 0 0 1 1 1 eTRIG0 pin 0 1 0 x x Reserved 0 1 1 0 0 eTPUA28 0 1 1 0 1 eTPUA29 0 1 1 1 0 eTPUA30 0 1 1 1 1 eTPUA31 1 0 0 0 0 eTPUB28 1 0 0 0 1 eTPUB29 1 0 0 1 0 eTPUB30...

Page 240: ...1 PIT3 Trigger 0 0 1 1 0 eTPUA30 0 0 1 1 1 eTRIG1 pin 0 1 0 x x Reserved 0 1 1 0 0 eTPUA28 0 1 1 0 1 eTPUA29 0 1 1 1 0 eTPUA30 0 1 1 1 1 eTPUA31 1 0 0 0 0 eTPUB28 1 0 0 0 1 eTPUB29 1 0 0 1 0 eTPUB30...

Page 241: ...1 PIT3 Trigger 0 0 1 1 0 Reserved 0 0 1 1 1 eTRIG0 pin 0 1 0 x x Reserved 0 1 1 0 0 eTPUA28 0 1 1 0 1 eTPUA29 0 1 1 1 0 eTPUA30 0 1 1 1 1 eTPUA31 1 0 0 0 0 eTPUB28 1 0 0 0 1 eTPUB29 1 0 0 1 0 eTPUB30...

Page 242: ...eTPU 24 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 7 19 eTPU Input Select Register SIU_ISEL8 Table 7 39 SIU_ISEL8 Bit Field Descriptions Field Description 0 11 Reserved 11 eTPU29 eTPU29 input sele...

Page 243: ...Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 eTSEL...

Page 244: ...1 1 eTPUA31 1 0 0 0 0 Reserved 1 0 0 0 1 Reserved 1 0 0 1 0 Reserved 1 0 0 1 1 Reserved 1 0 1 0 0 eMIOS10 AND PIT2 1 0 1 0 1 eMIOS10 AND PIT3 1 0 1 1 0 Reserved 1 0 1 1 1 Reserved 1 1 0 0 0 Reserved 1...

Page 245: ...l 24 0100 eTPUA Channel 25 12 15 HSELB Halt Input Select for Decimation Filter B 0000 Unused 0001 eTPUA Channel 22 0010 eTPUA Channel 23 0011 eTPUA Channel 24 0100 eTPUA Channel 25 16 19 ZSELC ZIR Inp...

Page 246: ...7 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R ZSELG HSELG ZSELH HSELH W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 7 42 SIU_DECFIL2 Bit Field Descriptions Field Description 0 3 ZSELE ZIR Input Select...

Page 247: ...tion Filter G 0000 Unused 0001 eTPUB Channel 18 0010 eTPUB Channel 19 0011 eTPUB Channel 20 0100 eTPUB Channel 21 24 27 ZSELH ZIR Input Select for Decimation Filter H 0000 Unused 0001 eTPUB Channel 18...

Page 248: ...Compare register match Holds the value of the match input signal to the SIU The match input is asserted if the values in SIU_CBRH and SIU_CBRL are the same as the public password stored in flash 0xFE...

Page 249: ...tf on this device and ENGCLK The ENGCLK frequency is divided from fplatf according to the following equation The maximum ENGCLK frequency is 66 MHz 132 MHz 2 Note Setting ENGDIV to 0 makes the ENGCLK...

Page 250: ...ernal clock CLKOUT Do not change EBDF during an external bus access or while an access is pending The CLKOUT frequency is divided from the system clock frequency according to the descriptions below Wh...

Page 251: ...0 0 0 0 Figure 7 24 Compare B Register Low SIU_CBRL Address SIU_BASE 0x9A0 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 2...

Page 252: ...Timer PIT_RTI for more information on how to use the SIU_HLT and SIU_HLTACK registers Figure 7 26 Halt Register SIU_HLT 24 26 Reserved 27 BYPASS Bypass bit 0 system clock divider is not bypassed 1 sy...

Page 253: ...Field Descriptions Table 7 46 SIU_HLT Register Field Descriptions Field Description 0 31 HLT Halt Selects The HLT bits halt specific modules Each bit corresponds to a separate module as mapped below 0...

Page 254: ...eld Descriptions Field Description 0 31 HLTACK Halt Acknowledge The HLTACK bits acknowledge halt for specific modules Each bit corresponds to a separate module as mapped below 0 CPU and platform1 1 rs...

Page 255: ...121 122 123 124 125 126 127 4 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 5 160 161 162 163 164 165 166 167 168 169...

Page 256: ...O 6 PGPDO 7 PGPDO 8 PGPDO 9 PGPDO 10 PGPDO 11 PGPDO 12 PGPDO 13 PGPDO 14 PGPDO 15 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R PGPDO 16 PGPDO 17 PGPDO 18 P...

Page 257: ...e pad interface signals data in corresponding to the external GPIO pin associated with the register 0 The value of the pad interface signals data in for the corresponding GPIO pin is logic low 1 The v...

Page 258: ...t of one of three on chip sources The sources on this device are the eTPU module eMIOS module or a software updated GPO data register The mapping between module or data register and the output frame f...

Page 259: ...9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Chan 7 6 5 4 3 2 1 0 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 0 1 2 3 4 5 6 7 Enable 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 260: ...tput High Register SIU_BASE 0x0D0C SIU_BASE 0x0D0F DSPIB GP Mask Output Low Register SIU_BASE 0x0D10 SIU_BASE 0x0D13 DSPIC GP Mask Output High Register SIU_BASE 0x0D14 SIU_BASE 0x0D17 DSPIC GP Mask Ou...

Page 261: ...12 DATA 13 DATA 14 DATA 15 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIU_BASE 0xD04 SIU_BASE 0xD0C SIU_BASE 0xD14 SIU_BASE 0xD1C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R W MASK 16 MASK 17 MASK 18 MASK 1...

Page 262: ...0 0 0 0 0 0 0 0 Table 7 54 SIU_ETPUBA Field Descriptions Field Description 0 31 ETPUBx ETPUB channel select 0 This bit in the DSPI_A serialized output frame will not use the respective ETPUB channel...

Page 263: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R DSPI AL 16 DSPI AL 17 DSPI AL 18 DSPI AL 19 DSPI AL 20 DSPI AL 21 DSPI AL 22 DSPI AL 23 DSPI AL 24 DSPI AL 25 DSPI AL...

Page 264: ...0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R EMIOS 23 EMIOS 15 EMIOS 14 EMIOS 13 EMIOS 12 EMIOS 11 EMIOS 10 EMIOS 9 EMIOS 8 EMIOS 6 EMIOS 5 EMIOS 4 EMIOS 3 EMIOS 2 EMIOS 1 EMIOS 0 W RESET 0...

Page 265: ...ETPUAx ETPUA channel select 0 This bit in the DSPI_C serialized output frame will not use the respective ETPUA channel 1 This bit in the DSPI_C serialized output frame will use the respective ETPUA c...

Page 266: ...0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R DSPI CL 16 DSPI CL 17 DSPI CL 18 DSPI CL 19 DSPI CL 20 DSPI CL 21 DSPI CL 22 DSPI CL 23 DSPI CL 24 DSPI CL 25 DSPI CL 26 DSPI CL 27 DSPI CL 28...

Page 267: ...output frame will not use the respective ETPUB channel 1 This bit in the DSPI_D serialized output frame will use the respective ETPUB channel SIU_BASE 0xD74 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0...

Page 268: ...the input state of an external GPIO pin Each byte of a register represents the input state of a single external GPIO pin The first 256 GPDIx_x registers corresponds to the same GPDI inputs described...

Page 269: ...s Drive strength selection for outputs Input buffer enable when direction is configured for output Input hysteresis enable disable Open drain push pull output selection Multiplexed function selection...

Page 270: ...et cycle is already being processed 7 4 3 External Interrupts There are 16 external interrupt inputs IRQ 0 IRQ 15 to the SIU The IRQ inputs can be configured for rising edge events falling edge events...

Page 271: ...it is cleared in the DMA Interrupt select register SIU_DIRSR The NMI pin function or platform SWT can generate either an NMI or a critical interrupt When WKPCFG_NMI_GPIO213 is enabled as NMI the pin w...

Page 272: ...sections for more information Section 7 3 1 4 External Interrupt Status Register SIU_EISR Section 7 3 1 7 Overrun Status Register SIU_OSR Section 7 3 1 8 Overrun Request Enable Register SIU_ORER 7 4...

Page 273: ...and word sized accesses The values read written to these parallel registers are coherent with the data read written to the SIU_GPDOx_x and SIU_GPDIx_x registers 7 4 5 Internal Multiplexing The interna...

Page 274: ...mand FIFO Trigger Source Select IMUX Select Registers SIU_ISEL4 7 For example you can select one of the following signals to source the ETRIG 0 input trigger for the eQADC TXDC_ETRIG 0 _GPIO 244 pin E...

Page 275: ...serialized output signal or the PCSD 2 deserialized output signal The remaining IRQ inputs are multiplexed in the same manner The inputs to the IRQ from each DSPI module are offset by one so that if m...

Page 276: ...one external SPI device thus reducing pin utilization of the device MCU In this example the SOUT and SIN of the two DSPIs connect to separate external SPI devices which share a common PCS and SCK To...

Page 277: ...ctor 7 95 PXR40 Microcontroller Reference Manual Rev 1 Figure 7 53 DSPI Parallel Chaining SOUT SOUT SIN SIN PCS 0 SS SCK SCK IN SS SCK IN SIN SOUT External SPI device SIN SCK IN SS SOUT External SPI d...

Page 278: ...System Integration Unit SIU 7 96 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...

Page 279: ...libration constants A description of their usage is provided in the Temperature Sensor Chapter The Unique Device ID is encoded and stored in four adjacent memory locations There is no specific user in...

Page 280: ...System Information Module PXR40 Microcontroller Reference Manual Rev 1 8 2 Freescale Semiconductor...

Page 281: ...lation for all internal MCU resources MMU configuration to boot user application compiled as Classic PowerPC Book E code or as Freescale VLE code Passes control to user application code in the interna...

Page 282: ...d out The development bus EBI boot mode can be used for application code development 9 4 Memory Map The BAM occupies 16 KB of memory space 0xFFFF_C000 to 0xFFFF_FFFF The actual code size of the BAM pr...

Page 283: ...am Flow Chart Reset Config MMU for internal boot BOOTCFG Y N Search for RCHW Found RCHW Y N Setup EBI and development bus pins for separate Check RCHW Found RCHW Y N Serial boot Exit To User Code 00 B...

Page 284: ...value as shown in Table 9 3 Depending on the values stored in the censorship word and serial boot control word in the shadow row of the internal flash memory the internal flash memory can be enabled o...

Page 285: ...Enabled Disabled Flash Internal Public 0x55AA Enabled Enabled Public Serial Flash Password 01 Don t care 0x55AA Enabled Disabled Flash Serial Public Password Any value except 0x55AA Disabled Enabled...

Page 286: ...t word after the RCHW must be programmed with the user application s starting address The BAM passes control to the user application at this starting address Table 9 6 provides possible RCHW locations...

Page 287: ...bit determines if the core software watchdog timer is enabled after passing control to the user application code 0 Disable core software watchdog timer 1 Enable core watchdog timer after reset The ti...

Page 288: ...If the BAM program finds a valid RCHW BOOT_BLOCK_ADDRESS is the address from Table 9 6 of the valid RCHW The BAM program fetches the application start address from BOOT_BLOCK_ADDRESS 0x4 The BAM bran...

Page 289: ...U system frequency EVTO pin is kept high during reset Baud Rate Detection serial boot mode allows communication with adaptable speed based on measured baud rate of the host transmission EVTO pin has t...

Page 290: ...equal to system frequency divided by 60 using the standard 11 bit identifier format detailed in CAN 2 0A specification See Table 9 8 for examples of baud rates Only one message buffer 0 is used for a...

Page 291: ...otocol The download protocol follows four steps 1 Host sends 64 bit password 2 Host sends start address size of download code in bytes and VLE bit 3 Host sends the application code data 4 The MCU swit...

Page 292: ...sword stored in the shadow row in internal flash memory c If SIU_CCR DISNEX is cleared the MCU is not considered to be censored and the password is compared to the fixed value of 0xFEED_FACE_CAFE_BEEF...

Page 293: ...boundary to the start address maximum 4 bytes The BAM also writes 0x0 to all memory locations from the last byte of data downloaded to the following 8 byte boundary maximum 7 bytes An additional 8 zer...

Page 294: ...SCI the host should send a zero byte as the test frame When booting through the CAN the host should send zero ID zero length message as the test frame The MCU requires some time to setup its communic...

Page 295: ...d shown in the Table 9 10 Table 9 9 Lookup Table for CAN Bit Timing Time quanta per bit Time segment 1 Time Segment 2 RJW PROPSEG PSEG1 PSEG2 8 1 3 3 2 9 2 3 3 2 10 3 3 3 2 11 4 3 3 2 12 3 4 4 2 13 4...

Page 296: ...t Mode The BAM program sets up EBI related registers as shown in the Table 9 12 RCHW PS0 must be programmed to 1 since the development bus does not support 32 bit port size in that sub mode Table 9 11...

Page 297: ...et Figure 9 8 shows the logic that enables access to Nexus clients in a censored device using the JTAG port Table 9 13 Development Bus EBI Register Settings multiplexed mode Register Function Value Co...

Page 298: ...shadow block 3 If there is a match the Nexus client TAP controller enters normal operation mode and the DISNEX flag in the SIU_CCR register is negated indicating Nexus is enabled Upon negation of rese...

Page 299: ...naccessible Also if code does not exist in the first bootable region of the internal flash to reprogram the shadow flash with the proper censorship control word and password the device will be in a ce...

Page 300: ...Boot Assist Module BAM 9 20 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...

Page 301: ...requests1 n1 Priority arbitrator n1 Highest priority interrupt requests n1 Request selector Lowest vector interrupt request n1 Vector encoder Interrupt vector 9 x 4 bits Interrupt acknowledge registe...

Page 302: ...ts programmable preemption This scheduling scheme is suitable for statically scheduled hard real time systems The INTC is optimized for a large number of interrupt requests Table 10 1 displays the int...

Page 303: ...greatest hexadecimal address IVPR 0x1DF0 that is available in the interrupt memory map for this device Because blocks of memory throughout the total memory map are used for other purposes the maximum...

Page 304: ...nterrupt requests i e by using application software to assert an interrupt request These same software configurable interrupt requests also can be used to break the work involved in servicing an inter...

Page 305: ...or prefix register IVPR is added to the offset contained in the external input interrupt vector offset register IVOR4 Note that since bits IVOR4 28 31 are not part of the offset value the vector offse...

Page 306: ...LIFO eases the calculation of the maximum stack depth at the cost of postponing the servicing of the next interrupt request 10 1 4 2 Hardware Vector Mode In hardware vector mode the interrupt exceptio...

Page 307: ...chapter for more information on how to configure these pins 10 3 Memory Map and Register Definition Table 10 2 is the INTC memory map NOTE To ensure compatibility with all Power Architecture devices...

Page 308: ...upt register 4 8 R W 0x00 10 3 1 5 10 1 2 Base 0x0025 INTC_SSCIR5 INTC software set clear interrupt register 5 8 R W 0x00 10 3 1 5 10 1 2 Base 0x0026 INTC_SSCIR6 INTC software set clear interrupt regi...

Page 309: ...figure options of the INTC Address Base 0x0000 INTC_MCR Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 310: ...or msync instruction is also necessary after accessing the resource but before lowering the PRI field Refer to Section 10 5 5 2 Ensuring Coherency 10 3 1 3 INTC Interrupt Acknowledge Register INTC_IAC...

Page 311: ...last pushed on the LIFO is popped into INTC_CPR The values and size of data Address Base 0x0010 INTC_IACKR Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 3...

Page 312: ...written to a pair SETn and CLRn bits at the same time CLRn is asserted regardless of whether CLRn was asserted before the write Although INTC_SSCIn is 8 bits wide it can be accessed with a single 16...

Page 313: ...is asserted 10 4 Functional Description 10 4 1 Interrupt Request Sources The INTC has two types of interrupt requests peripheral and software configurable The assignments between the interrupt reques...

Page 314: ...E ECSM_ESR FNCE ECSM combined interrupt requests Internal SRAM non correctable error Flash non correctable error eDMA2 A 0x00A0 10 EDMA_ERL ERR31 ERR0 eDMA_A channel error flags 31 0 0x00B0 11 EDMA_IR...

Page 315: ...INT28 eDMA_A channel interrupt 28 0x0280 40 EDMA_IRQRL INT29 eDMA_A channel interrupt 29 0x0290 41 EDMA_IRQRL INT30 eDMA_A channel interrupt 30 0x02A0 42 EDMA_IRQRL INT31 eDMA_A channel interrupt 31 P...

Page 316: ...R_A CIS1 eTPU engine A channel 1 interrupt status 0x0460 70 ETPU_CISR_A CIS2 eTPU engine A channel 2 interrupt status 0x0470 71 ETPU_CISR_A CIS3 eTPU engine A channel 3 interrupt status 0x0480 72 ETPU...

Page 317: ...ISR_A CIS28 eTPU engine A channel 28 interrupt status 0x0610 97 ETPU_CISR_A CIS29 eTPU engine A channel 29 interrupt status 0x0620 98 ETPU_CISR_A CIS30 eTPU engine A channel 30 interrupt status 0x0630...

Page 318: ...queue flag 0x07C0 124 EQADC_FISR4 CFFF eQADC A command FIFO 4 fill flag 0x07D0 125 EQADC_FISR4 RFDF eQADC A receive FIFO 4 drain flag 0x07E0 126 EQADC_FISR5 NCF eQADC A command FIFO 5 non coherency fl...

Page 319: ...F ESCIA_IFSR1 FE ESCIA_IFSR1 PF ESCIA_IFSR1 BERR ESCIA_IFSR2 RXRDY ESCIA_IFSR2 TXRDY ESCIA_IFSR2 LWAKE ESCIA_IFSR2 STO ESCIA_IFSR2 PBERR ESCIA_IFSR2 CERR ESCIA_IFSR2 CKERR ESCIA_IFSR2 FRC ESCIA_IFSR2...

Page 320: ...ister overflow Unrequested data received 0x0960 0x0970 150 151 Reserved FlexCAN A and FlexCAN C 0x0980 152 CANA_ESR BOFF_INT CANA_ESR TWRN_INT CANA_ESR RWRN_INT FlexCAN A bus off interrupt FlexCAN A t...

Page 321: ...rrupt 0x0B30 179 CANC_IFRL BUF3 FlexCAN C buffer 3 interrupt 0x0B40 180 CANC_IFRL BUF4 FlexCAN C buffer 4 interrupt 0x0B50 181 CANC_IFRL BUF5 FlexCAN C buffer 5 interrupt 0x0B60 182 CANC_IFRL BUF6 Fle...

Page 322: ...2 0x0D30 211 EDMA_IRQRH INT32 eDMA_A channel interrupt 32 0x0D40 212 EDMA_IRQRH INT33 eDMA_A channel interrupt 33 0x0D50 213 EDMA_IRQRH INT34 eDMA_A channel interrupt 34 0x0D60 214 EDMA_IRQRH INT35 eD...

Page 323: ...nterrupt 61 0x0F10 241 EDMA_IRQRH INT62 eDMA_A channel interrupt 62 0x0F20 242 EDMA_IRQRH INT63 eDMA_A channel interrupt 63 eTPU B 0x0F30 243 ETPU_CISR_B CIS0 eTPU engine B channel 0 interrupt status...

Page 324: ...TPU engine B channel 25 interrupt status 0x10D0 269 ETPU_CISR_B CIS26 eTPU engine B channel 26 interrupt status 0x10E0 270 ETPU_CISR_B CIS27 eTPU engine B channel 27 interrupt status 0x10F0 271 ETPU_C...

Page 325: ...rupt 0x1260 294 CANB_IFRL BUF11 FlexCAN B buffer 11 interrupt 0x1270 295 CANB_IFRL BUF12 FlexCAN B buffer 12 interrupt 0x1280 296 CANB_IFRL BUF13 FlexCAN B buffer 13 interrupt 0x1290 297 CANB_IFRL BUF...

Page 326: ...11 FlexCAN D buffer 11 interrupt 0x1430 323 CAND_IFRL BUF12 FlexCAN D buffer 12 interrupt 0x1440 324 CAND_IFRL BUF13 FlexCAN D buffer 13 interrupt 0x1450 325 CAND_IFRL BUF14 FlexCAN D buffer 14 interr...

Page 327: ...and FIFO 7 command queue end of queue flag 0x1930 403 EQADC_FISR1 CFFF eQADC B command FIFO 7 fill flag 0x1940 404 EQADC_FISR1 RFDF eQADC B receive FIFO 7 drain flag 0x1950 405 EQADC_FISR2 NCF eQADC B...

Page 328: ...INT04 eDMA_B channel interrupt 4 0x1AF0 431 EDMA_IRQRL INT05 eDMA_B channel interrupt 5 0x1B00 432 EDMA_IRQRL INT06 eDMA_B channel interrupt 6 0x1B10 433 EDMA_IRQRL INT07 eDMA_B channel interrupt 7 0...

Page 329: ...nel interrupt 31 0x1CA0 458 Reserved eMIOS 0x1CB0 459 EMIOS_GFR F24 eMIOS channel 24 flag 0x1CC0 460 EMIOS_GFR F25 eMIOS channel 25 flag 0x1CD0 461 EMIOS_GFR F26 eMIOS channel 26 flag 0x1CE0 462 EMIOS...

Page 330: ...t requests of eSCI module C LIN status register 1 LIN status register 2 SCI status register 2 Transmit data register empty Transmit complete Receive data register full Idle line Overrun Noise flag Fra...

Page 331: ...ates an interrupt request within the INTC just like a peripheral interrupt request An interrupt request is triggered by software writing a 1 to the SETn bit in INTC software set clear interrupt regist...

Page 332: ...vector encoder submodule If multiple interrupt requests from the priority arbitrator submodule are asserted then only the one with the lowest vector is passed as asserted to the vector encoder submodu...

Page 333: ...ities an ISR executing with PRI in the INTC_CPR equal to 15 is not preempted Therefore the LIFO supports the stacking of 15 priorities However the LIFO is only 14 entries deep An entry for a priority...

Page 334: ...iority of the preempted ISR the interrupt request for the preempted ISR or any other asserted peripheral or software configurable interrupt request at or below that priority does not cause a preemptio...

Page 335: ...5 Initialization and Application Information 10 5 1 Initialization Flow After exiting reset all of the PRIn fields in INTC priority select registers INTC_PSR0 INTC_PSR479 is zero and PRI in INTC curre...

Page 336: ...code to restore most of context required by e500 EABI Popping the LIFO after the restoration of most of the context and the disabling of processor recognition of interrupts eases the calculation of t...

Page 337: ...ar ensure store to clear flag bit has completed lis r3 INTC_EOIR ha form adjusted upper half of INTC_EOIR address li r4 0x0 form 0 to write to INTC_EOIR wrteei 0 disable processor recognition of inter...

Page 338: ...rity is high enough to cause preemption the INTC selects the one with the lowest unique vector regardless of the order in time that they asserted However the ability to meet deadlines with this schedu...

Page 339: ...nstead of disabling processor recognition of all interrupts eliminates the time when accessing a shared resource that all higher priority interrupts are blocked For example while ISR3 cannot preempt I...

Page 340: ...ar lower PRI 10 5 5 2 2 Raised Priority Preserved Before the instruction after the GetResource system service executes all pending transactions have completed These pending transactions can include an...

Page 341: ...terrupted E Interrupt exception handler prolog acknowledges interrupt by reading INTC_IACKR F PRI of 3 pushed onto LIFO PRI in INTC_CPR updates to 2 the priority of ISR208 G ISR208 clears its flag bit...

Page 342: ...lines that share a resource They do not need to use the PCP to access the shared resource 10 5 7 Software configurable Interrupt Requests The software configurable interrupt requests can be used in tw...

Page 343: ...second processor after accessing the block of data clears the corresponding CLRn bit and then writes 1 to a SETn bit on the first processor informing it that it now can access the block of data 10 5 8...

Page 344: ...g to INTC end of interrupt register INTC_EOIR as the clearing of the flag bit that caused the present ISR to be executed Refer to Section 10 4 3 1 2 End of Interrupt Exception Handler for more informa...

Page 345: ...rity of the preempting interrupt request If the processor recognition of interrupts is disabled during the LIFO restoration interrupt requests to the processor can go undetected However since the peri...

Page 346: ...Interrupts and Interrupt Controller INTC 10 46 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...

Page 347: ...th a separate power source for standby operation Byte halfword word and doubleword addressable 8 bit ECC 11 2 SRAM Operating Modes Table 11 1 lists and describes the SRAM operating modes 11 3 External...

Page 348: ...errors Detects 72 bit reads 64 bit data bus plus the 8 bit ECC that return all zeros or all ones asserts an error indicator on the bus cycle and sets the error flag SRAM does not detect all errors gr...

Page 349: ...ts the valid types of SRAM operations that can precede the current SRAM operation valid operation during the preceding clock Wait states Lists the number of wait states bus clocks the operation requir...

Page 350: ...ck all bits that require initialization after power on Use a 64 bit cache inhibited write to each SRAM location to initialize the SRAM array as part of the application initialization code All writes m...

Page 351: ...bits specify an even number of registers and write on 64 bit word aligned boundaries The following example code illustrates the use of the stmw instruction to initialize the SRAM ECC bits init_RAM li...

Page 352: ...General Purpose Static RAM SRAM 11 6 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...

Page 353: ...nction of the flash memory module is to serve as electrically programmable and erasable non volatile memory The NVM memory can be used for instruction and data storage The flash memory module contains...

Page 354: ...mming purposes are accessed through PBRIDGE_A Note The first 16 bytes of every 32 byte aligned row fall in Array A and the last 16 bytes fall in array B Flash_A array blocks 128 bits wide Flash_B arra...

Page 355: ...for 256 bit accesses and a prefetch controller are used to support single cycle read responses for hits in the buffers Hardware and software configurable read and write access protections on a per mas...

Page 356: ...s Shadow information stored in non volatile shadow block Independent program erase of the shadow block 12 1 3 Modes of Operation 12 1 3 1 Flash User Mode User mode is the default operating mode of the...

Page 357: ...0x0000_8000 L2 16K 128 0x0000_C000 L3 16K 128 0x0001_0000 L4 2 16K 128 0x0001_4000 L5 16K 128 0x0001_8000 L6 16K 128 0x0001_C000 L7 16K 128 0x0002_0000 L8 3 64K 128 0x0003_0000 L9 64K 128 0x0004_0000...

Page 358: ...FFF_FFFF 0x00FF_FDFC 0x00FF_FFFF General use Table 12 3 Flash Configuration Register Memory Map Offset from FLASH_REGS_ BASE 0xC3F8_8000 Register Bits Access Reset Value1 Section Page 0x0000 FLASH_A_M...

Page 359: ...13 12 27 0x0048 0x3FFF Reserved 0x4000 FLASH_B_MCR Module configuration register 32 R W 0x0000_0400 12 2 2 1 12 8 0x4004 FLASH_B_LMLR Low Mid address space block locking register 32 R W 12 2 2 2 12 1...

Page 360: ...are Reserved 8 Reserved 9 11 LAS 2 0 Low Address Space The value of the LAS field corresponds to the configuration of the Low Address Space LAS is read only 000 One 256 KB Blocks Flash_B 100 Eight 16...

Page 361: ...l state once the erase suspended program is completed PEAS is read only 0 Shadow address space is disabled for program erase and main address space enabled 1 Shadow address space is enabled for progra...

Page 362: ...entering a suspend state The module is in program suspend when PSUS 1 and DONE 1 PSUS can be set high only when PGM and EHV are high A 0 to 1 transition of PSUS starts the sequence which sets DONE and...

Page 363: ...sequence is not suspended 1 Erase sequence is suspended 31 EHV Enable High Voltage The EHV bit enables the flash module for a high voltage program erase operation EHV is cleared on reset EHV must be s...

Page 364: ...long with bits in the Secondary LLOCK FLASH_x_SLMLR determine if the block is locked from program or erase An OR of FLASH_x_LMLR and FLASH_x_SLMLR determine the final lock status NOTE A reset value of...

Page 365: ...information from the shadow block is loaded into the SLOCK register The SLOCK bit may be written as a register Reset causes the bits to go back to their shadow block value The default value of the SLO...

Page 366: ..._x_HLR register Figure 12 5 16 21 Reserved 22 31 LLOCK Low Address Space Block Lock A value of 1 in a bit of the lock register signifies that the corresponding block is locked for program and erase A...

Page 367: ...tus bit only and may not be written or cleared and the reset value is 0 The method to set this bit is to provide a password and if the password matches the HBE bit is set to reflect the status of enab...

Page 368: ...Table 12 8 Offset 0x000C 0x400C Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R SLE 0 0 0 0 0 0 0 0 0 0 SS LOCK 0 0 SM LOCK 0 0 0 0 0 0 S...

Page 369: ...2 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSEL 0 0 0 0 0 0 LSEL W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 12 7 FLASH_x_LMSR Register Table 12 9 FL...

Page 370: ...selected before doing an erase interlock write as part of the erase sequence The select register is not writable once an interlock write is completed until FLASH_x_MCR DONE is set at the completion o...

Page 371: ...ss captured during an ECC Event Error Single Bit Correction or State Machine operation The SAD register is not writable 0 Address Captured is from Main Array Space 1 Address Captured is from Shadow Ar...

Page 372: ...ardware reset 0 No prefetching may be triggered by this master 1 Prefetching may be triggered by this master Note These bits refer to the master ID not the master port number as shown in the following...

Page 373: ...N Data Prefetch Enable This field enables or disables prefetching initiated by a data read access This field is cleared by hardware reset 0 No prefetching is triggered by a data read access 1 Prefetch...

Page 374: ...FLASH_BIUAPR Table 12 13 FLASH_BIUAPR Bit Field Descriptions Field Description 0 1316 17 24 29 Reserved 14 15 18 23 30 31 MnAP Master n Access Protection where n represents the master ID number in th...

Page 375: ...The buffers can be organized as a pool of available resources or with a fixed partition between instruction and data buffers In all cases when a buffer miss occurs it is allocated to the least recent...

Page 376: ...table when the flash is put into UTest mode by writing a passcode Offset 0x0024 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R LBCFG 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 1 1 1 1 1 1 1 1...

Page 377: ...within the Flash Either a modified Hamming code is used or a modified Hsiao code is used 0 ECC is implemented with a modified Hamming algorithm 1 ECC is implemented with a modified Hsiao algorithm 25...

Page 378: ...AIE if the operation has finished AID 1 or aborted by clearing AIE if the operation is ongoing AID 0 AIE is not simultaneously writable to a 1 as UTI is being cleared to a 0 0 Array integrity checks a...

Page 379: ...logic by allowing data bits to be input into the ECC logic and then read out by doing array reads or array integrity checks The DAI 31 0 correspond to the 32 Array bits representing Word 0 of the doub...

Page 380: ...tten to do interlock writes Interlock writes attempted to invalid locations due to blocks that do not exist in non 2n array sizes will result in an interlock occurring but attempts to program or erase...

Page 381: ...ill selected ECC segments within the page The program operation consists of the following sequence of events 1 Change the value in the FLASH_x_MCR PGM bit from a 0 to a 1 NOTE Ensure the block that co...

Page 382: ...In the case of an erase suspended program the value in FLASH_x_MCR PEAS is retained from the erase An interlock write must be performed before setting FLASH_x_MCR EHV The user may terminate a program...

Page 383: ...PGM 0 User mode read state PEG 0 Read MCR DONE 1 DONE 0 Write MCR PSUS 0 EHV 1 Abort WRITE EHV 0 Step 5 Step 6 PEG Success PEG 1 Write MCR Failure PEG 0 Step 7 EHV 0 PGM more words Step 8 No Yes Writ...

Page 384: ...not suspended until FLASH_x_MCR DONE 1 At this time flash core reads may be attempted After it is suspended the flash core may be read only Reads to the blocks being programmed erased return indetermi...

Page 385: ...ASH_x_MCR EHV can be set to a 1 Data words written during erase sequence interlock writes are ignored The user may terminate the erase sequence by clearing FLASH_x_MCR ERS before setting FLASH_x_MCR E...

Page 386: ...array may be read or a program sequence may be initiated erase suspended program Before initiating a program sequence the user must first clear FLASH_x_MCR EHV If a program sequence is initiated the v...

Page 387: ...erase the main address space User mode read state Write MCR ERS 1 Select blocks Erase interlock write Step 1 Step 2 Step 3 Write MCR EHV 1 High voltage active Access MCR DONE Step 4 WRITE ESUS 1 Read...

Page 388: ...ll contain an illegal password and the debug port will be inaccessible Also if code does not exist in the first bootable region of the internal flash to reprogram the shadow flash with the proper cens...

Page 389: ...deliver vector and scalar results In addition to the base PowerPC Book E instruction set support the PXR40 core also implements the VLE variable length encoding technology providing improved code den...

Page 390: ...APU Status and Control Register SPR 512 SPEFSCR SPE EFPU Registers SPR 1016 L1FINV0 Machine Check Syndrome Register MCSR SPR 572 BTB Control1 SPR 1013 BUCSR BTB Register SPR 516 L1CFG1 SPR 1011 L1CSR...

Page 391: ...Cb2 PMLCb3 PMR 400 PMR 144 PMR 145 PMR 146 PMR 147 PMR 272 PMR 273 PMR 274 PMR 275 User Control read only UPMGC0 UPMLCa0 UPMLCa1 UPMLCa2 UPMLCa3 UPMLCb0 UPMLCb1 UPMLCb2 UPMLCb3 PMR 384 PMR 128 PMR 129...

Page 392: ...ysical translation for use in performing the cache tag compare If the physical address matches a valid cache tag entry the access hits in the cache For a read operation the cache supplies the data to...

Page 393: ...1 L1CSR0 Field Descriptions Field Description 0 3 WID Way Instruction Disable 0 The corresponding way in the instruction cache is available for replacement by instruction miss line fills 1 The corresp...

Page 394: ...0 Cache Error Injection is disabled 1 Parity errors will be purposefully injected into every byte subsequently written into the cache The parity bit of each 8 bit data element written will be inverte...

Page 395: ...ll replace an existing locked line with the requested line 25 26 DCEA Data Cache Error Action 00 Error Detection causes Machine Check exception 01 Error Detection causes Correction Auto invalidation N...

Page 396: ...egardless of the enable DCE value During cache invalidations the parity check bits are written with a value dependent on the DCEDT selection DCEDT should be written with the desired value for subseque...

Page 397: ...ing condition and will remain set until cleared by software writing 0 to this bit location 23 ICLFC Instruction Cache Lock Bits Flash Clear When written to a 1 a cache lock bits flash clear operation...

Page 398: ...ions require approximately 134 cycles to complete Invalidation occurs regardless of the enable ICE value During cache invalidations the parity check bits are written with a value dependent on the ICED...

Page 399: ...y and valid and then is invalidated 11 Reset way replacement pointer to the way indicated by CWAY 1 These bits are not implemented and should be written with zero for future compatibility 0 CWAY 0 CSE...

Page 400: ...enty three page sizes 1K 2K 4K 8K 16K 32K 64K 128K 256K 512K 1M 2M 4M 8M 16M 32M 64M 128M 256M 512M 1G 2G 4G Hardware assist for TLB miss exceptions Software managed by tlbre tlbwe tlbsx tlbsync and t...

Page 401: ...entry_id MAS1 MAS2 MAS3 result 13 4 4 TLB Write Entry Instruction tlbwe The TLB write entry instruction causes the contents of certain fields within the MMU assist registers MAS1 MAS2 and MAS3 to be w...

Page 402: ...13 4 5 2 MMU Control and Status Register 0 MMUCSR0 The MMU Control and Status Register 0 MMUCSR0 is a 32 bit register The SPR number for MMUCSR0 is 1012 in decimal MMUCSR0 controls the state of the MM...

Page 403: ...as zero and writes are ignored 30 TLB1_FI TLB1 flash invalidate 0 No flash invalidate 1 TLB1 invalidation operation When written to a 1 a TLB1 invalidation operation is initiated by hardware Once comp...

Page 404: ...22 23 24 25 26 27 28 29 30 31 SPR 625 Read Write Reset Unaffected Figure 13 8 MMU Assist Register 1 MAS1 Fields are defined below Table 13 7 MAS1 Descriptor Context and Configuration Control Field Co...

Page 405: ...10 64KB 0b00111 128KB 0b01000 256KB 0b01001 512KB 0b01010 1MB 0b01011 2MB 0b01100 4MB 0b01101 8MB 0b01110 16MB 0b01111 32MB 0b10000 64MB 0b10001 128MB 0b10010 256MB 0b10011 512MB 0b10100 1GB 0b10101 2...

Page 406: ...Required 0 Memory Coherence is not required 1 Memory Coherence is required 30 G Guarded 0 Access to this page are not guarded and can be performed before it is known if they are required by the seque...

Page 407: ...UW SW UR SR 0 TLBSELD 01 0 TIDSELD 0 TSIZED 0 VLED WD ID MD GD ED 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SPR 628 Read Write Reset Unaffected Figure 13 1...

Page 408: ...writes are ignored 0 SPID 0 SAS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SPR 630 Read Write Reset Unaffected Figure 13 12 MMU Assist Register 6 MAS6 Fields...

Page 409: ...ead Write Reset 0x0 Figure 13 13 Exception Syndrome Register ESR Table 13 12 ESR Bit Settings Field Description Associated Interrupt Type 0 3 Reserved 4 PIL Illegal Instruction exception Program 5 PPR...

Page 410: ...und Exception Data Storage Data TLB Instruction Storage Alignment Program System Call 27 29 Reserved 30 MIF Misaligned Instruction Fetch Instruction Storage Instruction TLB 31 Reserved 0 UCLE SPE 0 WE...

Page 411: ...te 0 The processor is in supervisor mode can execute any instruction and can access any resource e g GPRs SPRs MSR etc 1 The processor is in user mode cannot execute any privileged instruction and can...

Page 412: ...entry 1 The processor directs all data storage accesses to address space 1 TS 1 in the relevant TLB entry 28 Reserved1 29 PMM PMM Performance monitor mark bit System software can set PMM when a marke...

Page 413: ...n Icache miss with an uncorrectable lock error occurred May also be set on locked line refill error Status 8 DC_LKERR Data Cache Lock error Indicates a cache control operation or invalidation operatio...

Page 414: ...red 1 The Exception Type indicates the exception type associated with a given syndrome bit Error Report indicates that this bit is only set for error report exceptions which cause machine check interr...

Page 415: ...et field of the IVOR selected for a particular interrupt type is concatenated with the value held in the Interrupt Vector Prefix register IVPR to form an instruction address from which execution is to...

Page 416: ...ists register settings when a Critical Input interrupt is taken Table 13 15 IVOR Register Fields Field Description 0 15 Reserved 16 27 Vector Offset Vector Offset This field is used to provide a quadw...

Page 417: ...13 9 2 1 Machine Check Causes Machine check causes are divided into different types Error Report Machine Check conditions Non Maskable Interrupt NMI machine check exceptions Asynchronous machine chec...

Page 418: ...ebug APU is disabled Clearing of DE is optionally supported by control in HID0 when the Debug APU is enabled Table 13 18 Data Storage Interrupt Register Settings Register Setting Description SRR0 Set...

Page 419: ...the exception is enabled by MSREE it takes the External Input interrupt Table 13 19 ISI Exceptions and Conditions Interrupt Type Interrupt Vector Offset Register Causing Conditions Instruction Storage...

Page 420: ...ord aligned The operand of lwarx or stwcx not word aligned The operand of lharx or sthcx not halfword aligned Execution of a dcbz instruction is attempted with a disabled cache Execution of a dcbz ins...

Page 421: ...d DCR specified The PXR40 will invoke a Privileged Instruction program exception on attempted execution of the following instructions when MSRPR 1 user mode A privileged instruction mtspr and mfspr in...

Page 422: ...Set to the effective address of the excepting instruction SRR1 Set to the contents of the MSR at the time of the interrupt MSR UCLE 0 SPE 0 WE 0 CE EE 0 PR 0 FP 0 ME FE0 0 DE FE1 0 IS 0 DS 0 PMM 0 RI...

Page 423: ...elected bits in the Time Base register changing from 0 to 1 A Fixed Interval Timer interrupt occurs when no higher priority exception exists a FIT exception exists TSRFIS 1 and the interrupt is enable...

Page 424: ...Watchdog Timer interrupt is taken Table 13 26 Fixed Interval Timer Interrupt Register Settings Register Setting Description SRR0 Set to the effective address of the instruction that the processor wou...

Page 425: ...r settings when an ITLB interrupt is taken DEAR Unchanged Vector IVPR0 15 IVOR1216 27 4b0000 1 DE is cleared when the Debug APU is disabled Clearing of DE is optionally supported by control in HID0 wh...

Page 426: ...no higher priority exception exists a Debug exception exists in the Debug Status Register and Debug interrupts are enabled both DBCR0IDM 1 internal debug mode and MSRDE 1 MSR UCLE 0 SPE 0 WE 0 CE EE...

Page 427: ...PT CIRPT DCNT or DEVT type exception set to the effective address of the instruction that the processor would have attempted to execute next if no exception conditions were present CSRR1 DSRR1 Set to...

Page 428: ...Floating point Data interrupt is taken Table 13 31 SPE EFPU Unavailable Interrupt Register Settings Register Setting Description SRR0 Set to the effective address of the excepting SPE EFPU instruction...

Page 429: ...dicates an overflow For a performance monitor interrupt to be signaled on an enabled condition or event PMGC0PMIE must be set Although an exception condition may occur with MSREE 0 the interrupt canno...

Page 430: ...ructions have completed before the wait instruction completes causes processor instruction fetching to cease and ensures that no subsequent instructions are initiated until an asynchronous interrupt o...

Page 431: ...1 These instructions are available in VLE instruction pages to perform a multiple register load or store to a word aligned memory address 13 10 3 Performance Monitor The performance monitor provides t...

Page 432: ...Core e200z7 Overview PXR40 Microcontroller Reference Manual Rev 1 13 44 Freescale Semiconductor...

Page 433: ...sted by more than one master port arbitration logic selects the higher priority master and grant it ownership of the slave port All other masters requesting that slave port are stalled until the highe...

Page 434: ...with programmable priorities and attributes Table 14 1 XBAR Switch Ports Module Port Master ID Type Number e200z7 core0 CPU instruction Master 0 0 e200z7 core0 Data Master 1 0 Nexus 3 8 eDMA_A Master...

Page 435: ...R0 Master priority register for slave port 0 32 R W 0x7654_3210 14 2 1 1 14 4 Base 0x0004 0x000F Reserved Base 0x0010 XBAR_SGPCR0 General purpose control register for slave port 0 32 R W 0x0000_0000 1...

Page 436: ...e master has been assigned high priority by a slave NOTE Masters must be assigned unique priority levels The master priority register can only be accessed in supervisor mode with 32 bit accesses After...

Page 437: ...must be cleared 5 7 MSTR6 Master 6 priority Set the arbitration priority for master port 6 on the associated slave port 000 Master 6 has the highest priority when accessing slave port n 101 Master 6...

Page 438: ...access a slave not being accessed by another master because it is not parked on any master The XBAR_SGPCR can only be accessed in supervisor mode with 32 bit accesses After the RO read only bit is set...

Page 439: ...slave port s registers can be written 1 All this slave port s registers are read only and cannot be written attempted writes have no effect and result in an error response 1 21 Reserved must be clear...

Page 440: ...ich master port this slave port parks on when no masters are actively making requests PCTL must be set to 0b00 000 Park on master port 0 001 Park on master port 1 010 Invalid value 011 Invalid value 1...

Page 441: ...trol of the slave port it is targeting it is wait stated A master is given control of a targeted slave port only after a previous access to a different slave port has completed regardless of its prior...

Page 442: ...slave port A master access is responded to with an error if the access decodes to a location not occupied by a slave port This is the only time the XBAR directly responds with an error response All ot...

Page 443: ...umber of the last master to perform a transfer on the slave bus The highest priority requesting master becomes the owner of the slave bus at the next transfer boundary accounting for fixed length burs...

Page 444: ...specific master mode is selected the slave port parks on the master designated by the PARK field When the master accesses the slave port again a one clock arbitration penalty is incurred only for an...

Page 445: ...elects for peripheral devices on the slave bus interface 15 1 1 Block Diagram The PBRIDGE is the interface between the system bus and on chip peripherals as shown in Figure 15 1 Figure 15 1 PBRIDGE In...

Page 446: ...ed areas in the table do not apply Refer to Section 12 2 2 9 Flash Bus Interface Access Protection Register FLASH_BIUAPR in the Flash chapter for more information on access protection Table 15 1 Perip...

Page 447: ...face is only meant for slave peripherals PBRIDGE B Slave 7 PBRIDGE B XBAR MPU SWT STM ESCM eDMA control INTC eQADC A eQADC B Decimation Filter A Decimation Filter B Decimation Filter C Decimation Filt...

Page 448: ...s is shown in Table 15 2 Table 15 2 PBRIDGE A Memory Map Address Register Bits Access Reset Value Section Page Base 0xC3F0_0000 PBRIDGE_A_MPCR Master privilege control register 32 R W 0x7777_7777 15 3...

Page 449: ...e 0x0024 PBRIDGE_B_PACR1 Peripheral access control register 1 32 R W 0x5444_4444 15 3 1 2 15 7 Base 0x0028 PBRIDGE_B_PACR2 Peripheral access control register 2 32 R W 0x5444_4444 15 3 1 2 15 7 Base 0x...

Page 450: ...gisters 15 3 1 1 Master Privilege Control Register PBRIDGE_x_MPCR The master privilege control register PBRIDGE_x_MPCR specifies 4 bit access fields defining the access privilege level associated with...

Page 451: ...whether the PBRIDGE is enabled to buffer writes from the master Buffered writes are disabled by default 0 Buffered write accesses from the master are disabled 1 Buffered write accesses from the master...

Page 452: ...Address Base 0x0020 PBRIDGE_x_PACR0 Base 0x0024 PBRIDGE_B_PACR1 Base 0x0028 PBRIDGE_B_PACR2 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R BW0 1 SP0 2 WP0 TP0 2 BW1 SP1 WP1 TP1 BW2 SP2 WP2 TP2 BW...

Page 453: ...Determines whether write accesses to this peripheral are allowed to be buffered Write accesses not bufferable by default 0 No write accesses are bufferable by the PBRIDGE to this peripheral 1 Write ac...

Page 454: ...ct Determines whether the peripheral allows accesses from an untrusted master Only trusted master privileges can access this register 0 Accesses from an untrusted master are allowed 1 Accesses from an...

Page 455: ...x0020 0 PBRIDGE B 0b0101 1 XBAR 0b0100 2 3 Reserved 0b0000 4 MPU 0b0100 5 7 Reserved 0b0000 PBRIDGE_B_PACR1 PBRIDGE_B_Base 0x0024 0 5 Reserved 0b0000 6 SWT 0b0100 7 STM 0b0100 PBRIDGE_B_PACR2 PBRIDGE_...

Page 456: ...B_OPACR2 PBRIDGE_B_Base 0x0048 0 FlexCAN A 0b0100 1 FlexCAN B 0b0100 2 FlexCAN C 0b0100 3 FlexCAN D 0b0100 4 7 Reserved 0b0100 PBRIDGE_B_OPACR3 PBRIDGE_B_Base 0x004C 0 FlexRay 0b0100 1 2 Reserved 0b01...

Page 457: ...while terminating the system bus access early This provides improved performance in systems where frequent writes to a slow peripheral occur Write buffering is controllable on a per master and per per...

Page 458: ...d completed in order on the slave interface regardless of buffering If the buffer is full a following write cycle stalls until it can either be buffered if bufferable or can be initiated If the buffer...

Page 459: ...es are allowed In addition peripherals can be designated as write protected The PBRIDGE supports the notion of trusted masters for security purposes Masters can be individually designated as trusted f...

Page 460: ...Peripheral Bridge PBRIDGE 15 16 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...

Page 461: ...ransactions and evaluates the appropriateness of each transfer Memory references with sufficient access control rights are allowed to complete but references that are not mapped to any region descript...

Page 462: ...slave modules The Master IDs of all bus master modules are also shown as their values are required to configure certain MPU registers described in this chapter Table 16 1 XBAR Switch Ports Module MPU...

Page 463: ...e descriptor Alternate memory view of the access control word for each descriptor provides an efficient mechanism to dynamically alter the access rights of a descriptor only For overlapping region des...

Page 464: ...R0 MPU error address register MPU port 0 32 R 1 16 2 2 2 16 7 0x0014 MPU_EDR0 MPU error detail register MPU port 0 32 R 1 16 2 2 3 16 7 0x0018 MPU_EAR1 MPU error address register MPU port 1 32 R 1 16...

Page 465: ...AC3 MPU RGD alternate access control 3 32 W 1 16 2 2 5 16 13 0x0810 MPU_RGDAAC4 MPU RGD alternate access control 4 32 W 1 16 2 2 5 16 13 0x0814 MPU_RGDAAC5 MPU RGD alternate access control 5 32 W 1 16...

Page 466: ...MPU for signaling the presence of a captured error contained in the MPU_EARn and MPU_EDRn registers The individual bit is set when the hardware detects an error and records the faulting address and a...

Page 467: ...rresponding bit in the MPU_CESR SPERR field 20 23 NRGD Number of Region Descriptors This 4 bit read only field specifies the number of region descriptors implemented in the MPU The defined encodings i...

Page 468: ...r When an error is detected the hit qualified access control vector is captured in this field If the MPU_EDRn register contains a captured error and the EACD field is all zeroes this signals an access...

Page 469: ...ffset MPU_BASE 0x400 16 n 0x0 MPU_RGDn Word0 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R SRTADDR 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0...

Page 470: ...an instruction fetch and the operating mode supervisor user of the requesting processor For non processor data movement engines bus masters 4 7 the evaluation logic simply uses hwrite to determine if...

Page 471: ...mask defined in MPU_RGDn Word3 are to be included in the region hit evaluation If cleared the region hit evaluation does not include the process identifier Note See Table 16 1 for the MPU Master ID l...

Page 472: ...to these locations do not affect the descriptor s valid bit Offset MPU_BASE 0x400 16 n 0xc MPU_RGDn Word3 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26...

Page 473: ...DAACn Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 M6RE M6WE M5RE M5WE M4RE M4WE 0 0 0 0 0 0 0 0 W Reset n 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 Reset n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 474: ...rivilege Violation Determination While the access evaluation macro is making the region hit determination the logic is also evaluating if the current access is allowed by the permissions defined in th...

Page 475: ...eDMA source or destination error occurs in the eDMA controller which can be enabled to provide an interrupt request through the INTC If the error was caused by a FlexRay access a controller host inte...

Page 476: ...r masters or while in user mode terminated with an error 5 When the MPU detects an access error the current AHB bus cycle is terminated with an error response and information on the faulting reference...

Page 477: ...issions while CP1 has r r permission in this space Both DMA engines are excluded from this shared processor data region The overlapping spaces between RGD3 and RGD4 defines another shared data space t...

Page 478: ...Memory Protection Unit MPU 16 18 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...

Page 479: ...ication is set that the error occurred A non correctable ECC error is generated when two or more bits in a 64 bit doubleword are incorrect Non correctable ECC errors cause an interrupt and if enabled...

Page 480: ...RSR Misc Reset Status 8 RO 0x00 17 2 2 4 17 4 0x0010 0x0042 Reserved 0x0043 ECSM_ECR ECC configuration register 8 R W 0x00 17 2 2 5 17 5 0x0047 ECSM_ESR ECC status register 8 R W 0x00 17 2 2 6 17 6 0x...

Page 481: ...nd no change to the targeted register Table 17 2 ECSM Graphical Memory Map ECSM Offset Register 0x0000 Processor Core Type ECSM_PCT Revision ECSM_REV 0x0008 IPS Module Configuration ECSM_IMC 0x000C Re...

Page 482: ...is defined by a module input signal it can only be read from the peripheral programming model Any attempted write is ignored A 0 indicates a peripheral module connection to decoded slot n is absent A...

Page 483: ...ion register definition 2 SWTR Platform Software Watchdog Timer Reset 1 Last recorded event was a reset caused by the platform s software watchdog timer 3 7 Reserved Offset ECSM_BASE_ADDR 0x0043 Acces...

Page 484: ...he ECSM_ESR and verify the current contents matches the original contents If the two values are different repeat from step one 4 When the values are identical write a 1 to the asserted ECSM_ESR flag t...

Page 485: ...M_REAT and ECSM_REDR registers To clear this interrupt flag write a 1 to this bit Writing a 0 has no effect 0 No reportable single bit RAM correction has been detected 1 A reportable single bit RAM co...

Page 486: ...rsion The assertion of this bit forces the RAM controller to create one 1 bit data inversion as defined by the bit position specified in ERRBIT on the first write operation after this bit is set The n...

Page 487: ...ler but then the polarity of the bit position defined by ERRBIT and the overall odd parity bit are inverted to introduce a 2 bit ECC error in the RAM After this bit has been enabled to generate a sing...

Page 488: ...ted write is ignored See Figure 17 6 and Table 17 8 for the flash ECC master number register definition Offset ECSM_BASE_ADDR 0x0050 Access User read only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R FEAR...

Page 489: ...he ECSM_FEDR is a 64 bit register for capturing the data associated with the last properly enabled ECC event in the flash memory Depending on the state of the ECC configuration register an ECC event i...

Page 490: ...s read only any attempted write is ignored See Figure 17 10 and Table 17 11 for the RAM ECC address register definition Offset ECSM_BASE_ADDR 0x0058 Access User read only 0 1 2 3 4 5 6 7 8 9 10 11 12...

Page 491: ...ted This register is read only any attempted write is ignored See Figure 17 11 and Table 17 12 for the RAM ECC syndrome register definition Offset ECSM_BASE_ADDR 0x0060 Access User read only 0 1 2 3 4...

Page 492: ...Error ECSM_ RESR 0 7 Data Bit in Error 0x00 No Error 0x4F DATA 32 0xA4 DATA 41 0x01 ECC 0 0x52 DATA 34 0xA7 DATA 42 0x02 ECC 1 0x54 DATA 35 0xA8 DATA 43 0x04 ECC 2 0x57 DATA 36 0xAB DATA 44 0x08 ECC 3...

Page 493: ...the last properly enabled ECC event in the RAM memory Depending on the state of the ECC configuration register an ECC event in the RAM causes the address attributes and data associated with the access...

Page 494: ...rrectable ECC error is undefined This register is read only any attempted write is ignored See Figure 17 15 and Table 17 16 for the RAM ECC data register definition Table 17 15 ECSM_REAT Field Descrip...

Page 495: ...U U U U U U U U U U U U U U 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R REDR 48 63 W Reset U U U U U U U U U U U U U U U U Figure 17 15 RAM ECC Data Low ECSM_REDRL Register Table 17 16 REDR Fiel...

Page 496: ...Error Correction Status Module ECSM 17 18 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...

Page 497: ...errupt status bit so the ISR software can determine if the critical interrupt request came from the SWT or the external critical interrupt pin WKPCFG_GPIO213 The SWT can assert a reset when the watchd...

Page 498: ...n the SWT_MCR SWT_TO SWT_WN SWT_SK registers are read only 18 3 1 Memory Map The SWT memory map are shown in Table 18 1 The base address for each SWT is given in Table 18 1 18 3 2 Register Description...

Page 499: ...ixed sequence 0xA602 0xB480 is used to service the watchdog 1 Keyed Service Mode two pseudorandom key values are used to service the watchdog 23 RIA Reset on Invalid Access 0 Invalid access to the SWT...

Page 500: ...Control Allows the watchdog timer to be stopped when the device enters stop mode 0 SWT counter continues to run in stop mode 1 SWT counter is stopped in stop mode 30 FRZ Debug Mode Control Allows the...

Page 501: ...2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIF W Reset...

Page 502: ...R Field Description 0 31 WTO Watchdog time out period in clock cycles An internal 32 bit down counter is loaded with this value or 0x100 which ever is greater when the service sequence is written or w...

Page 503: ...4 Functional Description for details Otherwise the sequence 0xA602 followed by 0xB480 is written to the WSC field To clear the soft lock bit SWT_MCR SLK the value 0xC520 followed by 0xD928 is written...

Page 504: ...iptions Offset 0x018 Access Read Write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SK1 NOTES 1 If neither HLK or SLK lock bi...

Page 505: ...e SWT_SR WSC field There is no timing requirement between the two writes The unlock sequence logic ignores service sequence writes and recognizes the 0xC520 0xD928 sequence regardless of previous writ...

Page 506: ...diately on a time out If the SWT_MCR ITR bit is set an initial time out causes the SWT to generate an interrupt and load the down counter with the time out period If the service sequence is not writte...

Page 507: ...interrupt node Three channels sharing the same interrupt node Independent interrupt source for each channel Counter can be stopped in debug mode 19 1 3 Modes of Operation The STM supports two device m...

Page 508: ...ister 32 R W 0x0000_0000 19 3 2 5 5 0x001C Reserved 0x0020 STM_CCR1 STM Channel 1 Control Register 32 R W 0x0000_0000 19 3 2 3 4 0x0024 STM_CIR1 STM Channel 1 Interrupt Register 32 R W 0x0000_0000 19...

Page 509: ...0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R CPS 0 0 0 0 0 0 FRZ TEN W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 19 1 STM Control Registe...

Page 510: ...CNT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 19 2 STM Count Register STM_CNT Field Description 0 31 CNT Timer count value used as the time base for all channels W...

Page 511: ...26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CIF W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 19 4 STM Channel Interrupt Register STM_CIRn Field Description 0 30 Reserved 31 CIF Channel Interru...

Page 512: ...STM_CR TEN bit When enabled in normal mode the counter continuously increments When enabled in debug mode the counter operation is controlled by the STM_CR FRZ bit When the STM_CR FRZ bit is set the c...

Page 513: ...ntroduction 20 1 1 Overview This section describes the function of the Periodic Interrupt Timer block PIT_RTI The PIT is an array of timers that can be used to generate interrupts It also provides a d...

Page 514: ...block are Timers can be configured to generate interrupts All interrupts are maskable Independent timeout periods for each timer and RTI RTI can be used to generate a CPU wake up interrupt RTI clock...

Page 515: ...3 2 5 6 0x100 PIT_CH0_LDVAL Channel 0 load value register 32 R W 0x0000_0000 20 3 2 2 5 0x104 PIT_CH0_CVAL Channel 0 current value register 32 R 0x0000_0000 20 3 2 3 5 0x108 PIT_CH0_TCTRL Channel 0 ti...

Page 516: ...r 32 R 0x0000_0000 20 3 2 3 5 0x138 PIT_CH3_TCTRL Channel 3 timer control register 32 R W 0x0000_0000 20 3 2 4 5 0x13C PIT_CH3_TFLAG Channel 3 timer channel flag register 32 R W 0x0000_0000 20 3 2 5 6...

Page 517: ...Hn_LDVAL Field Descriptions Field Description 0 31 TSV Time Start Value Bits These bits set the timer start value The timer counts down until it reaches 0 then it generates an interrupt and loads this...

Page 518: ...0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIE TEN W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 20 5 Timer Control Register PIT_RTI_TCTRL PIT_CHn_TCTR...

Page 519: ...s in the TCTRL registers A new interrupt can be generated only after the previous one is cleared If desired the current counter value of the timer can be read via the CVAL registers Offset channel_bas...

Page 520: ...iting the LDVAL register with the new load value This value is loaded after the next trigger counter reaches 0 event see Figure 20 9 Figure 20 7 Stopping and Starting a Timer Figure 20 8 Modifying Run...

Page 521: ...PITCTRL register The 50 MHz clock frequency equates to a clock period of 20 ns Timer 1 needs to trigger every 5 12 ms 20 ns 256000 cycles The value for the LDVAL register trigger would be calculated...

Page 522: ...ion on multiple modules with a single 32 bit write however using the SIU_HALT function also disables R W function on the peripheral registers for additional power saving 20 5 2 2 Low Power Mode With R...

Page 523: ...re operation as desired In some cases where periodic operation is preferred the interrupt handler may perform a set of tasks and then write the SIU_HALT register mask and re enter the low power mode b...

Page 524: ...Periodic Interrupt Timer PIT_RTI 20 12 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...

Page 525: ...second generation platform block capable of performing complex data movements through n programmable channels n 64 for eDMA_A n 32 for eDMA_B with minimal intervention from the host processor The har...

Page 526: ...transfers with minimal intervention from a host processor 32 bytes of data registers used as temporary storage to support burst transfers refer to SSIZE bit Connections to the crossbar switch for bus...

Page 527: ...gether to form a single error interrupt 32 channel eDMA or two error interrupts 64 channel eDMA Support for scatter gather DMA processing Support for complex data structures Any channel can be program...

Page 528: ...of eDMA_x EDMA_A_BASE 0xFFF4_4000 EDMA_B_BASE 0xFFF5_4000 Table 21 1 eDMA Memory Map Offset from EDMA_x_BASE Register Bits Access Reset Value Section Page 0x0000 EDMA_x_MCR eDMA module control regist...

Page 529: ...priority register 8 R W 0x00 21 3 2 17 21 33 0x0101 EDMA_x_CPR1 eDMA channel 1 priority register 8 R W 0x01 21 3 2 17 21 33 0x0102 EDMA_x_CPR2 eDMA channel 2 priority register 8 R W 0x02 21 3 2 17 21...

Page 530: ...R W 0x1E 21 3 2 17 21 33 0x011F EDMA_x_CPR31 eDMA channel 31 priority register 8 R W 0x1F 21 3 2 17 21 33 0x0120 EDMA_A_CPR32 eDMA channel 32 priority register 8 R W 0x20 21 3 2 17 21 33 0x0121 EDMA_...

Page 531: ...2 priority register 8 R W 0x3E 21 3 2 17 21 33 0x013F EDMA_A_CPR63 eDMA channel 63 priority register 8 R W 0x3F 21 3 2 17 21 33 0x0140 0x0FFF Reserved 0x1000 EDMA_x_TCD00 eDMA transfer control descrip...

Page 532: ...56 R W 1 21 3 2 18 21 34 0x13C0 EDMA_x_TCD30 eDMA transfer control descriptor 30 256 R W 1 21 3 2 18 21 34 0x13E0 EDMA_x_TCD31 eDMA transfer control descriptor 31 256 R W 1 21 3 2 18 21 34 0x1400 EDMA...

Page 533: ...x1760 EDMA_A_TCD59 eDMA transfer control descriptor 59 256 R W 1 21 3 2 18 21 34 0x1780 EDMA_A_TCD60 eDMA transfer control descriptor 60 256 R W 1 21 3 2 18 21 34 0x17A0 EDMA_A_TCD61 eDMA transfer con...

Page 534: ...eDMA Channel 6 Priority EDMA_A_CPR6 eDMA Channel 7 Priority EDMA_A_CPR7 0xFFF4_4108 eDMA Channel 8 Priority EDMA_A_CPR8 eDMA Channel 9 Priority EDMA_A_CPR9 eDMA Channel 10 Priority EDMA_A_CPR10 eDMA...

Page 535: ...EDMA_A_CPR53 eDMA Channel 54 Priority EDMA_A_CPR54 eDMA Channel 55 Priority EDMA_A_CPR55 0xFFF4_4138 eDMA Channel 56 Priority EDMA_A_CPR56 eDMA Channel 57 Priority EDMA_A_CPR57 eDMA Channel 58 Priorit...

Page 536: ...Reserved 0xFFF5_4100 eDMA Channel 0 Priority EDMA_B_CPR0 eDMA Channel 1 Priority EDMA_B_CPR1 eDMA Channel 2 Priority EDMA_B_CPR2 eDMA Channel 3 Priority EDMA_B_CPR3 0xFFF5_4104 eDMA Channel 4 Priority...

Page 537: ...ample EDMA_A_ERQRH has upper 32 channels of eDMA_A 32 bits for eDMA_B 21 3 2 1 eDMA Control Register EDMA_x_MCR The 32 bit EDMA_x_MCR defines the basic operating configuration of the eDMA The eDMA arb...

Page 538: ...pletion When minor loop offsets are enabled the minor loop offset MLOFF is added to the final source address SADDR or to the final destination address DADDR or to both addresses prior to the addresses...

Page 539: ...ntrol Register EDMA_B_CR Table 21 4 EDMA_A_MCR Field Descriptions Field Description 0 13 Reserved 14 CXFR Cancel Transfer 0 Normal operation 1 Cancel the remaining data transfer Stop the executing cha...

Page 540: ...el arbitration before being activated again Upon minor loop completion the channel is active again if that channel has a minor loop channel link enabled and the link channel is itself This effectively...

Page 541: ...ported when the scatter gather operation begins at major loop completion A minor loop channel link configuration error is reported when the link operation is serviced at minor loop completion If a sys...

Page 542: ...DAE DOE NCE SGE SBE DBE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 21 4 eDMA Error Status Register EDMA_x_ESR Table 21 5 EDMA_x_ESR Field Descriptions Field Description 0 VLD Valid Bit Logical OR...

Page 543: ...etected in the EDMA_x_TCD DADDR field indicating EDMA_x_TCD DADDR is inconsistent with EDMA_x_TCD DSIZE 27 DOE Destination Offset Error 0 No destination offset configuration error 1 The last recorded...

Page 544: ...cess User R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R ERQ 63 ERQ 62 ERQ 61 ERQ 60 ERQ 59 ERQ 58 ERQ 57 ERQ 56 ERQ 55 ERQ 54 ERQ 53 ERQ 52 ERQ 51 ERQ 50 ERQ 49 ERQ 48 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 545: ...vers channels 31 0 The state of any given channel s error interrupt enable is directly affected by writes to these registers it is also affected by writes to the EDMA_x_SEEIR and EDMA_x_CEEIR The EDMA...

Page 546: ...0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R EEI 15 EEI 14 EEI 13 EEI 12 EEI 11 EEI 10 EEI 09 EEI 08 EEI 07 EEI 06 EEI 05 EEI 04 EEI 03 EEI 02 EEI 01 EEI 00 W Reset 0 0 0 0 0 0...

Page 547: ...QRH or EDMA_x_ERQRL to be set Setting bit 1 SERQ 0 provides a global set function forcing the entire contents of EDMA_A_ERQRH and EDMA_x_ERQRL to be asserted Reads of this register return all zeroes I...

Page 548: ...o be cleared Setting bit 1 CERQ 0 provides a global clear function forcing the entire contents of EDMA_A_ERQRH and EDMA_x_ERQRL to be zeroed disabling all eDMA request inputs Reads of this register re...

Page 549: ...EDMA_x_EEIRL to be set Setting bit 1 SEEI 0 provides a global set function forcing the entire contents of EDMA_A_EEIRH or EDMA_x_EEIRL to be asserted Reads of this register return all zeroes If bit 0...

Page 550: ...RL to be zeroed disabling error interrupts for all channels Reads of this register return all zeroes If bit 0 is set the CEEI command is ignored This allows multiple byte registers to be written as a...

Page 551: ...mapped mechanism to clear a given bit in the EDMA_A_ERH or EDMA_x_ERL to disable the error condition flag for a given channel The given value on a register write causes the corresponding bit in the E...

Page 552: ...s allows multiple byte registers to be written as a 32 bit word Reads of this register return all zeroes Offset EDMA_x_BASE 0x001D Access User write only 0 1 2 3 4 5 6 7 R 0 0 0 0 0 0 0 0 W NOP CERR 0...

Page 553: ...f this register return all zeroes Table 21 14 EDMA_x_SSBR Field Descriptions Field Description 0 NOP No operation 0 Normal operation 1 No operation ignore bits 1 7 1 7 SSB Set START Bit channel servic...

Page 554: ...the EDMA_A_IRQRH or EDMA_x_IRQRL a 1 in any bit position clears the corresponding channel s interrupt request A 0 in any bit position has no effect on the corresponding channel s current interrupt sta...

Page 555: ...e contents of this register can also be polled and a non zero value indicates the presence of a channel error regardless of the state of the EDMA_x_EEIR The EDMA_x_ESR VLD bit is a logical OR of all b...

Page 556: ...16 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R ERR 15 ERR 14 ERR 13 ERR 12 ERR 11 ERR 10 ERR 09 ERR 08 ERR 07 ERR 06 ERR 05 ERR 04 ERR 03 ERR 02 ERR 01 ER...

Page 557: ...through 15 When read the GRPPRI bits of the EDMA_x_CPRn register reflect the current priority level of the group of channels in which the corresponding channel resides GRPPRI bits are not affected by...

Page 558: ...fining the desired data movement operation The channel descriptors are stored in the local memory in sequential order channel 0 channel Address EDMA_x_BASE 0x0100 n Access User read write 0 1 2 3 4 5...

Page 559: ...urrent major iteration count citer Signed destination address offset doff 0x1000 32 x n 0x0018 Last destination address adjustment scatter gather address dlast_sga 0x1000 32 x n 0x001c Beginning major...

Page 560: ...ate value for the queue freezing the desired number of upper address bits The value programmed into this field specifies the number of lower address bits that are allowed to change For this circular q...

Page 561: ...sfer 96 127 0xC 0 31 SLAST Last source address adjustment Adjustment value added to the source address at the completion of the outer major iteration count This value can be applied to restore the sou...

Page 562: ...o be loaded into this channel This channel reload is performed as the major iteration count completes The scatter gather address must be 0 modulo 32 byte otherwise a configuration error is reported 22...

Page 563: ...the CITER count reaches zero it is cleared by software or hardware when the channel is activated when the DMA engine has begun processing the channel not when the first data transfer occurs Note This...

Page 564: ...this flag is set the eDMA hardware automatically clears the corresponding EDMA_A_ERQH or EDMA_x_ERQL bit when the current major iteration count reaches zero 0 The channel s EDMA_A_ERQH or EDMA_x_ERQL...

Page 565: ...puts are also connected to this module via the control logic Control This module provides all the control functions for the DMA engine For data transfers where the source and destination sizes are equ...

Page 566: ...nel number is sent through the address path and converted into the required address to access the TCD local memory Next the TCD memory is accessed and the required descriptor read from the local memor...

Page 567: ...TCD for example SADDR DADDR CITER If the outer major iteration count is exhausted then there are additional operations performed These include the final address adjustments and reloading of the BITER...

Page 568: ...error interrupts in the EDMA_x_EEIRL and or EDMA_x_EEIRH registers if desired 4 Write the 32 byte TCD for each channel that may request service 5 Enable any hardware service requests via the EDMA_x_ER...

Page 569: ...f the major loop is exhausted further post processing is executed for example interrupts major loop channel linking and scatter gather operations if enabled Figure 21 28 shows how each DMA request ini...

Page 570: ...oop 2 DMA request Minor loop 1 Major loop xADDR Starting address xSIZE Size of one data Minor loop NBYTES in minor loop often the same value as xSIZE Offset xOFF Number of bytes added to current addre...

Page 571: ...group 3 Group 0 is the next highest priority and has two channels with the same priority level 4 If group 1 has any service requests those requests are executed 5 After all of group 1 requests have c...

Page 572: ...ain Flag EQADC_A_FISR4_CFFF4 8 EQADC_A FISR4 CFFF4 EQADC_A Command FIFO 4 Fill Flag EQADC_A_FISR4_RFDF4 9 EQADC_A FISR4 RFDF4 EQADC_A Receive FIFO 4 Drain Flag EQADC_A_FISR5_CFFF5 10 EQADC_A FISR5 CFF...

Page 573: ...6 Flag eMIOS_GFR_F7 37 EMIOS GFR F7 eMIOS channel 7 Flag eMIOS_GFR_F10 38 EMIOS GFR F10 eMIOS channel 10 Flag eMIOS_GFR_F11 39 EMIOS GFR F11 eMIOS channel 11 Flag eMIOS_GFR_F16 40 EMIOS GFR F16 eMIOS...

Page 574: ...QADC_B_FISR1_RFDF1 3 EQADC_B FISR1 RFDF1 EQADC_B Receive FIFO 1 Drain Flag EQADC_B_FISR2_CFFF2 4 EQADC_B FISR2 CFFF2 EQADC_B Command FIFO 2 Fill Flag EQADC_B_FISR2_RFDF2 5 EQADC_B FISR2 RFDF2 EQADC_B...

Page 575: ...ERF_OB 23 DECFILTERF OB Decimation Filter F Output Buffer Drain Flag DECFILTERG_IB 24 DECFILTERG IB Decimation Filter G Input Buffer Fill Flag DECFILTERG_OB 25 DECFILTERG OB Decimation Filter G Output...

Page 576: ...group in the sequence or skipping a group if it has no pending requests If a channel requests service at a rate that equals or exceeds the round robin service rate then that channel is always serviced...

Page 577: ...D BITER 1 The data transfer begins after the channel service request is acknowledged and the channel is selected to execute After the transfer is complete the EDMA_x_TCD DONE bit is set and an interru...

Page 578: ...or loop complete 6 eDMA engine writes EDMA_x_TCD SADDR 0x1000 EDMA_x_TCD DADDR 0x2000 EDMA_x_TCD CITER 1 EDMA_x_TCD BITER 7 eDMA engine writes EDMA_x_TCD ACTIVE 0 EDMA_x_TCD DONE 1 EDMA_x_IRQRn 1 8 Th...

Page 579: ...f the minor loop 6 eDMA engine writes EDMA_x_TCD SADDR 0x1010 EDMA_x_TCD DADDR 0x2010 EDMA_x_TCD CITER 1 7 eDMA engine writes EDMA_x_TCD ACTIVE 0 8 The channel retires one iteration of the major loop...

Page 580: ...upper address bits 0x1234567x retain their original value In this example the source address is set to 0x12345670 the offset is set to 4 bytes and the mod field is set to 4 allowing for a 24 byte 16 b...

Page 581: ...D START bit is cleared automatically when the channel begins execution regardless of how the channel was activated 21 5 6 2 Active Channel TCD Reads The eDMA will read back the true EDMA_x_TCD SADDR E...

Page 582: ...ould be made For example with the initial fields of EDMA_x_TCD CITER E_LINK 1 EDMA_x_TCD CITER LINKCH 0xC EDMA_x_TCD CITER value 0x4 EDMA_x_TCD MAJOR E_LINK 1 EDMA_x_TCD MAJOR LINKCH 0x7 will execute...

Page 583: ...k was made before the channel retired The following coherency model is recommended when executing a dynamic channel link or dynamic scatter gather request 1 Set the EDMA_x_TCD MAJOR E_LINK bit 2 Read...

Page 584: ...ductor PXR40 Microcontroller Reference Manual Rev 1 NOTE The user must clear the EDMA_x_TCD DONE bit before writing the EDMA_x_TCD MAJOR E_LINK or EDMA_x_TCD E_SG bits The EDMA_x_TCD DONE bit is clear...

Page 585: ...in T The actual length of a cycle in T for the ideal controller 0 ppm EBI External Bus Interface FlexRay Memory Memory Window to store message buffer payload header status and synchronization frame re...

Page 586: ...main components Controller host interface CHI Protocol engine PE Clock domain crossing unit CDC A block diagram of the controller with its surrounding modules is given in Figure 22 1 MTS Media Access...

Page 587: ...for asynchronous PE and CHI clock domains The controller stores the frame header and payload data of frames received or of frames to be transmitted in the flexray memory The application accesses the f...

Page 588: ...or flexible and efficient message buffer implementation consistent data access ensured by means of buffer locking scheme application can lock multiple buffers at the same time size of message buffer p...

Page 589: ...nal power modes of the controller 22 1 6 1 Disabled Mode The controller enters the Disabled Mode during hard reset The controller indicates that it is in the Disabled Mode by negating the module enabl...

Page 590: ...ignals FR_A_RX FR_A_TX and FR_A_TX_EN are available on each package option The availability of the other off chip signals depends on the package option 22 2 1 Detailed Signal Descriptions This section...

Page 591: ...I is derived from the system bus clock and has the same phase and frequency as the system bus clock Since the FlexRay protocol requires data delivery at fixed points in time the memory read cycles fro...

Page 592: ...emory Base Address High Register SYMBADHR R W 0x0006 System Memory Base Address Low Register SYMBADLR R W 0x0008 Strobe Signal Control Register STBSCR R W 0x000A Reserved R 0x000C Message Buffer Data...

Page 593: ...Register SFIDAFMR R W Network Management Vector 0x004C Network Management Vector Register 0 NMVR0 R 0x004E Network Management Vector Register 1 NMVR1 R 0x0050 Network Management Vector Register 2 NMV...

Page 594: ...eive FIFO Message ID Acceptance Filter Value Register RFMIDAFVR R W 0x0092 Receive FIFO Message ID Acceptance Filter Mask Register RFMIAFMR R W 0x0094 Receive FIFO Frame ID Rejection Filter Value Regi...

Page 595: ...er 0 MBCCFR0 R W 0x0104 Message Buffer Frame ID Register 0 MBFIDR0 R W 0x0106 Message Buffer Index Register 0 MBIDXR0 R W 0x04F8 Message Buffer Configuration Control Status Register 127 MBCCSR127 R W...

Page 596: ...ster description for each register affected 22 5 2 2 3 Internal Register Access The following memory mapped registers are used to access multiple internal registers Strobe Signal Control Register STBS...

Page 597: ...mber The module version number is derived from the CHI version number and the PE version number 22 5 2 4 Module Configuration Register MCR This register defines the global configuration of the control...

Page 598: ...e controlled by the SCM bit and is given Table 22 9 SFFE Synchronization Frame Filter Enable This bit controls the filtering for received synchronization frames For details see Section 22 6 15 Sync Fr...

Page 599: ...RX FR_B_TX and FR_A_TX_EN driven by controller connected to FlexRay channel B 1 1 ports FR_A_RX FR_A_TX and FR_A_TX_EN driven by controller connected to FlexRay channel A ports FR_B_RX FR_B_TX and FR_...

Page 600: ...ddress for the receive FIFO if the FIFO address mode bit MCR FAM is set to 1 It is defines as a byte address Base 0x0008 16 bit write access required Write Anytime 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1...

Page 601: ...0x4 slot start A pulse 0 MT start 5 0x5 B 6 0x6 receive data after glitch filtering A value 4 FR_A_RX 7 0x7 B FR_B_RX 8 0x8 channel idle indicator A level 5 FR_A_RX 9 0x9 B FR_B_RX 10 0xA syntax error...

Page 602: ...1 This field defines the message buffer number of the last individual message buffer that is assigned to the first message buffer segment The individual message buffers in the first segment correspond...

Page 603: ...accepted by the PE When the application issues a protocol control command while the BSY bit is asserted the controller ignores this command sets the protocol command ignored error flag PCMI_EF in the...

Page 604: ...egister 0 PIFR0 and Protocol Interrupt Flag Register 1 PIFR1 is asserted and the related interrupt enable flag is asserted too The controller generates the combined protocol interrupt request if the P...

Page 605: ...MTD 0 both the interrupt flag MBIF and the interrupt enable bit MBIE in the corresponding Message Buffer Configuration Control Status Registers MBCCSRn are equal to 1 The application can not clear th...

Page 606: ...y The fatal protocol errors are 1 pLatestTx violation as described in the MAC process of the FlexRay protocol 2 transmission across slot boundary violation as described in the FSP process of the FlexR...

Page 607: ...eached MXS_IF Max Sync Frames Detected Interrupt Flag This flag is set when the number of synchronization frames detected in the current communication cycle exceeds the value of the node_sync_max fiel...

Page 608: ...1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 22 12 Protocol Interrupt Flag Register 1 PIFR1 Table 22 18 PIFR1 Field Descriptions Field Description EMC_IF Error Mode Changed Inte...

Page 609: ...CCL _IE MXS _IE MTX _IE LTXB _IE LTXA _IE TBVB _IE TBVA _IE TI2 _IE TI1 _IE CYS _IE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 22 13 Protocol Interrupt Enable Register 0 PIER0 Table 22 19 PIER0 F...

Page 610: ...s LTXA_IF interrupt request generation 0 interrupt request generation disabled 1 interrupt request generation enabled TBVB_IE Transmission across boundary on channel B Interrupt Enable This bit contro...

Page 611: ...terrupt request generation enabled PSC_IE Protocol State Changed Interrupt Enable This bit controls PSC_IF interrupt request generation 0 interrupt request generation disabled 1 interrupt request gene...

Page 612: ...Error Flag This flag is set when an overrun of the FIFO for channel A occurred This error occurs if a semantically valid frame was received on channel A and matches the all criteria to be appended to...

Page 613: ...igured in the corresponding protocol configuration register field payload_length_static in the Protocol Configuration Register 19 PCR19 0 No such error occurred 1 Static payload length error occurred...

Page 614: ...cription TBIVEC Transmit Buffer Interrupt Vector This field provides the number of the lowest numbered enabled transmit message buffer that has its interrupt status flag MBIF and its interrupt enable...

Page 615: ...24 CBSERCR Field Descriptions Field Description STATUS_ERR_CNT Channel Status Error Counter This field provides the current channel status error count The counter value is updated within the first ma...

Page 616: ...p mechanism 000 UNDEFINED 001 RECEIVED_HEADER 010 RECEIVED_WUP 011 COLLISION_HEADER 100 COLLISION_WUP 101 COLLISION_UNKNOWN 110 TRANSMITTED 111 reserved Base 0x002A Additional Reset CSAA CSP CPN RUN C...

Page 617: ...POC normal active state was reached from POC startup state via noisy leading cold start path HHR Host Halt Request Pending protocol related variable vPOC CHIHaltRequest This status bit is set when co...

Page 618: ...yntaxError for symbol window on channel B This status bit is set when a syntax error was detected during the symbol window on channel B 0 No such event 1 Syntax error detected MTB Media Access Test Sy...

Page 619: ...the configured value of either max_without_clock_correction_fatal or max_without_clock_correction_passive as defined in the Protocol Configuration Register 8 PCR8 The controller resets this counter on...

Page 620: ...s are detected in the communication slots the symbol window and the NIT 0 No boundary violation detected 1 Boundary violation detected AACA Aggregated Additional Communication on Channel A This flag i...

Page 621: ...cle Base 0x0032 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 CYCCNT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 22 24 Cycle Counter Register CYCTR Table 22 30 CYCTR Field Description...

Page 622: ...ot in the current communication cycle Base 0x0038 Additional Reset RUN Command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R RATECORR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 22 27 Rate Correction Val...

Page 623: ...ntioned in the Global Interrupt Flag and Enable Register GIFER Base 0x003A Additional Reset RUN Command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R OFFSETCORR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figur...

Page 624: ...eceive FIFO Channel A Almost Full Interrupt Flag Provides the same value as GIFER FAFAIF RBIF Receive Message Buffer Interrupt Flag This flag is set if for at least one of the individual receive messa...

Page 625: ...3 14 15 R SFEVB SFEVA SFODB SFODA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 22 31 Sync Frame Counter Register SFCNTR Table 22 37 SFCNTR Field Descriptions Field Description SFEVB Sync Frames Chan...

Page 626: ...ed to lock and unlock the odd cycle tables 0 No effect 1 Triggers lock unlock of the odd cycle tables CYCNUM Cycle Number This field provides the number of the cycle in which the currently locked tabl...

Page 627: ...Write only one pair of enabled Sync Frame Tables into flexray memory SDVEN Sync Frame Deviation Table Enable This bit controls the generation of the Sync Frame Deviation Tables The application must s...

Page 628: ...Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 22 35 Sync Frame ID Acceptance Filter Value Register SFIDAFVR Table 22 41 SFIDAFVR Field Descriptions Field Description FVAL Filter Value This field defin...

Page 629: ...ter defines the length of the network management vector in bytes Table 22 43 NMVR 0 5 Field Descriptions Field Description NMVP Network Management Vector Part The mapping between the Network Managemen...

Page 630: ...ble 22 46 TICCR Field Descriptions Field Description T2_CFG Timer T2 Configuration This bit configures the timebase mode of Timer T2 0 T2 is absolute timer 1 T2 is relative timer T2_REP Timer T2 Repet...

Page 631: ...lication modifies the value in this register while the timer is running the change becomes effective immediately and timer T1 will expire according to the changed value Base 0x005C Write Anytime 0 1 2...

Page 632: ...omes effective when the timer has expired according to the old values 22 5 2 43 Timer 2 Configuration Register 1 TI2CR1 Base 0x0060 Write Anytime 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R R T2_CYC_VAL R...

Page 633: ...ot status selection registers SSSR0 to SSSR3 Each internal registers selects a slot or symbol window NIT whose status vector will be saved in the corresponding Slot Status Registers SSR0 SSR7 accordin...

Page 634: ...er This field specifies the number of the slot whose status will be saved in the corresponding slot status registers Note If this value is set to 0 the related slot status register provides the status...

Page 635: ...The counter is restricted to valid frames only SYF Sync Frame Restriction This bit is used to restrict the counter to received frames with the sync frame indicator bit set to 1 0 The counter is not r...

Page 636: ...2 55 SSR0 SSR7 Field Descriptions Field Description VFB Valid Frame on Channel B protocol related variable vSS ValidFrame channel B 0 vSS ValidFrame 0 1 vSS ValidFrame 1 SYB Sync Frame Indicator Chann...

Page 637: ...A protocol related variable vRF Header NFIndicator channel A 0 vRF Header NFIndicator 0 1 vRF Header NFIndicator 1 SUA Startup Frame Indicator Channel A protocol related variable vRF Header SuFIndica...

Page 638: ...CR3 Field Descriptions Field Description SLOTSTATUSCNT Slot Status Counter This field provides the current value of the Slot Status Counter Base 0x0080 Write MTE Anytime CYCCNTMSK CYCCNTVAL POC config...

Page 639: ...L 0 0 0 0 RSBIDX W WMD Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 22 50 Receive Shadow Buffer Index Register RSBIR Table 22 59 RSBIR Field Descriptions Field Description WMD Write Mode This bit cont...

Page 640: ...High Register RFSYMBADHR Base 0x00EA Write Disabled Mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R SMBA 15 4 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 22 52 Receive FIFO System Memory Base...

Page 641: ...ster Receive FIFO Start Index Register RFSIR Receive FIFO Depth and Size Register RFDSR Receive FIFO Message ID Acceptance Filter Value Register RFMIDAFVR Receive FIFO Message ID Acceptance Filter Mas...

Page 642: ...0 0 0 0 0 0 0 0 0 Figure 22 56 Receive FIFO Depth and Size Register RFDSR Table 22 65 RFDSR Field Descriptions Field Description FIFO_DEPTHA FIFO_DEPTHB FIFO Depth This field defines the depth of the...

Page 643: ...10 11 12 13 14 15 R 0 0 0 0 0 0 RDIDX W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 22 58 Receive FIFO B Read Index Register RFBRIR Table 22 67 RFBRIR Field Descriptions Field Description RDIDX Read...

Page 644: ...mask for the message ID acceptance filter of the selected FIFO For details on message ID filtering see Section 22 6 9 9 FIFO Filtering Base 0x0090 Write POC config 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1...

Page 645: ...22 6 9 9 FIFO Filtering Base 0x0094 Write POC config 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 FIDRFVALA FIDRFVALB W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 22 62 Receive FIFO Frame ID R...

Page 646: ...4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 F3MD F2MD F1MD F0MD 0 0 0 0 F3EN F2EN F1EN F0EN W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 22 65 Receive FIFO Range Filter Control Register RFRFCTR Table 2...

Page 647: ...er 0 disabled 1 range filter 0 enabled Base 0x009C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 LASTDYNTXSLOTA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 22 66 Last Dynamic Slot Channel A Reg...

Page 648: ...nPointOffset 1 MT 6 tss_transmitter gdTSSTransmitter gdBit 5 wakeup_symbol_rx_idle gdWakeupSymbolRxIdle gdBit 5 wakeup_symbol_rx_low gdWakeupSymbolRxLow gdBit 3 wakeup_symbol_rx_window gdWakeupSymbolR...

Page 649: ...ycle pdMaxDrift T 24 25 micro_per_cycle_max pMicroPerCycle pdMaxDrift T 26 27 micro_per_macro_nom_half round pMicroPerMacroNom 2 T 7 offset_correction_out pOffsetCorrectionOut T 9 rate_correction_out...

Page 650: ...3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 macro_after_first_static_slot W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 22 69 Protocol Configuration Register 1 PCR1 Base 0x00A4 Write POC config 0 1 2 3 4 5...

Page 651: ...3 14 15 R 0 symbol_window_after_action_point macro_initial_offset_a W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 22 74 Protocol Configuration Register 6 PCR6 Base 0x00AE Write POC config 0 1 2 3 4 5...

Page 652: ...col Configuration Register 10 PCR10 Base 0x00B6 Write POC config 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R key_ slot_ used_ for_ start up key_ slot_ used_ for_ sync offset_correction_start W Reset 0 0 0...

Page 653: ...4 PCR14 Base 0x00BE Write POC config 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R listen_timeout 15 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 22 83 Protocol Configuration Register 15 PCR15 Base 0x00...

Page 654: ...00C8 Write POC config 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R micro_initial_offset_b micro_initial_offset_a W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 22 88 Protocol Configuration Register 20 PCR2...

Page 655: ...0D2 Write POC config 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R micro_per_cycle_min 15 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 22 93 Protocol Configuration Register 25 PCR25 Base 0x00D4 Write PO...

Page 656: ...DT bit and 1 to the LCKT bit no write access to the other bits is performed Base 0x00DA Write POC config 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R extern_offset_ correction minislots_max W Reset 0 0 0 0...

Page 657: ...es whether the message buffer will generate an interrupt request when its MBIF flag is set 0 Interrupt request generation disabled 1 Interrupt request generation enabled Message Buffer Status DUP Data...

Page 658: ...ntrol the receive and transmit behavior of the message buffer according to Table 22 81 CCFE Cycle Counter Filtering Enable This control bit is used to enable and disable the cycle counter filtering 0...

Page 659: ...this field depends on the message buffer transfer type Receive Message Buffer This field is used as a filter value to determine if the message buffer is used for reception of a message received in a s...

Page 660: ...buffers The physical message buffers are located in the flexray memory The structure of a physical message buffer is depicted in Figure 22 103 A physical message buffer consists of two fields the mess...

Page 661: ...of the slot status is provided in Section 22 6 5 2 3 Slot Status Description 22 6 2 2 Message Buffer Data Field The message buffer data field is a contiguous area of 2 byte entities This field contai...

Page 662: ...al Message Buffer Structure 22 6 3 1 1 Individual Message Buffer Segments The set of the individual message buffers can be split up into two message buffer segments using the Message Buffer Segment Si...

Page 663: ...ted message buffer header field in the flexray memory is determined according to Equation 22 4 SADR_MBHF RSBIR RSBIDX 10 SMBA Eqn 22 4 The length required for the message buffer data field depends on...

Page 664: ...eive FIFO A Read Index Register RFARIR Receive FIFO B Read Index Register RFBRIR The system memory base address SMBA is defined by the system memory base address register selected by the FIFO address...

Page 665: ...n configuration data for individual message buffers is located in the following registers Message Buffer Data Size Register MBDSR The MBSEG2DS and MBSEG1DS fields define the minimum length of the mess...

Page 666: ...ssociated with this message buffer 22 6 3 5 Individual Message Buffer Control Data During normal operation each individual message buffer can be controlled by the control and trigger bits CMT LCKT EDT...

Page 667: ...POP Count Register RFFLPCR 22 6 3 7 3 Receive FIFO Status Data The current status of the receive fifo is provided in the following register Global Interrupt Flag and Enable Register GIFER Receive FIF...

Page 668: ...um 64 Kbytes Each region start at a 16 byte boundary Message Buffer Header Area FlexRay Memory Message Buffer Data Area Sync Frame Table Area Data Field Offset Frame Header Slot Status Data Field Offs...

Page 669: ...6 Eqn 22 7 2 The start byte address SADR_MBHF of each message buffer header field for the FIFO must fulfill Equation 22 8 SADR_MBHF i 10 SYMDARD SMBA 0 i 1024 Eqn 22 8 FIFO Header Area FIFO FlexRay Me...

Page 670: ...t fulfill Equation 22 11 SADR_MBHF i 10 RFSYMBADR SMBA 0 i 1024 Eqn 22 11 2 The message buffer header fields for each FIFO have to be a contiguous area 22 6 4 6 Message Buffer Data Area The message bu...

Page 671: ...frame received regardless of whether the frame is valid or not For transmit message buffers the application writes the frame header of the frame to be transmitted into this location The frame header w...

Page 672: ...he value of the FID field must be equal to the value of the corresponding Message Buffer Frame ID Registers MBFIDRn If the controller detects a mismatch while transmitting the frame header it will set...

Page 673: ...of the received frame stored in the message buffer CYCCNT Cycle Count This is the number of the communication cycle in which the frame stored in the message buffer was received PLDLEN Payload Length T...

Page 674: ...he slot status structure for receive message buffers depends on the message buffer type and on the channel assignment for individual receive message buffers as given by Table 22 87 The meaning of the...

Page 675: ...e Indicator Channel B protocol related variable vRF Header NFIndicator channel B 0 vRF Header NFIndicator 0 1 vRF Header NFIndicator 1 SUB Startup Frame Indicator Channel B protocol related variable v...

Page 676: ...r NFIndicator 1 SUA Startup Frame Indicator Channel A protocol related variable vRF Header SuFIndicator channel A 0 vRF Header SuFIndicator 0 1 vRF Header SuFIndicator 1 SEA Syntax Error on Channel A...

Page 677: ...tocol related variable vRF Header SuFIndicator channel B 0 vRF Header SuFIndicator 0 1 vRF Header SuFIndicator 1 SEB Syntax Error on Channel B protocol related variable vSS SyntaxError channel B 0 vSS...

Page 678: ...Error on Channel A protocol related variable vSS SyntaxError channel A 0 vSS SyntaxError 0 1 vSS SyntaxError 1 CEA Content Error on Channel A protocol related variable vSS ContentError channel A 0 vS...

Page 679: ...s restrictions given in Table 22 92 22 6 6 Individual Message Buffer Functional Description The controller provides three basic types of individual message buffers 1 Single Transmit Message Buffers 2...

Page 680: ...nfigures the size of the two segments of individual message buffers by writing the message buffer number of the last message buffer in the first segment into the LAST_MB_SEG1 field in the Message Buff...

Page 681: ...uffers A single transmit message buffer is used by the application to provide message data to the controller that will be transmitted over the FlexRay Bus The controller uses the transmit message buff...

Page 682: ...20 A description of the states is given in Table 22 96 which also provides the access scheme for the access regions The status bits MBCCSRn EDS and MBCCSRn LCKS provide the application with the requir...

Page 683: ...Assigned Applications access to data control and status Message buffer assigned to next static slot CCNf 1 0 NF Null Frame Transmission Header is used for null frame transmission HLckCCNf 1 1 MSG NF...

Page 684: ...S If the command triggers the lock transition HL and the message buffer is in the state CCTx the lock transition has no effect command is ignored and message buffer state is not changed In this case t...

Page 685: ...sage buffer data field is described in Section 22 6 3 1 Individual Message Buffers As indicated by Table 22 96 the application shall write to the message buffer data field and change the commit bit CM...

Page 686: ...is example the message buffer with message buffer number n is Idle at the start of the search slot matches the slot and cycle number of the next slot and message buffer data are valid i e MBCCSRn CMT...

Page 687: ...bed in Section 22 6 7 Individual Message Buffer Search the controller triggers the slot assigned transition SA for up to two transmit message buffers if at least one of the conditions mentioned above...

Page 688: ...s the status updated transition SU With the SU transition the controller sets the message buffer interrupt flag MBCCSn MBIF to indicate the successful message transmission Depending on the transmissio...

Page 689: ...the null frame transmission is not changed at all The slot status field is not updated the status and control flags are not changed and the interrupt flag is not set 22 6 6 3 Receive Message Buffers...

Page 690: ...tions in order to ensure data consistency The receive message buffer states are given in Figure 22 128 A description of the message buffer states is given in Table 22 96 which also provides the access...

Page 691: ...is 0 0 CFG Disabled Message Buffer under configuration Excluded from message buffer search HDisLck 0 1 CFG Disabled and Locked Message Buffer under configuration Excluded from message buffer search HL...

Page 692: ...on at a time There is no need to specify priorities among them As shown in Table 22 104 the module transitions have a higher priority than the application transitions For all states except the CCRx st...

Page 693: ...n slot the received frame data are written into the shadow buffers For details on receive shadow buffers see Section 22 6 6 3 5 Receive Shadow Buffers Concept The data and status of the receive messag...

Page 694: ...s defined by the Message Buffer Segment Size and Utilization Register MBSSUTR Table 22 105 Receive Message Buffer Update vSS ValidFrame vRF Header NFIndicator Update description 1 1 Valid non null fra...

Page 695: ...ept is to ensure that only syntactically and semantically valid received non null frames are presented to the application in a receive message buffer The basic structure of a receive shadow buffer is...

Page 696: ...ata to the FlexRay bus The two sides are located in adjacent individual message buffers The message buffer that implements the commit side has an even message buffer number 2n The transmit side messag...

Page 697: ...in Figure 22 132 A description of the states is given in Table 22 108 The states for the transmit side of a Table 22 106 Double Transmit Message Buffer Access Regions Description Access Description Re...

Page 698: ...e commit side of a double transmit message buffer is given in Table 22 107 Table 22 107 Double Transmit Message Buffer State Description Commit Side State MBCCSR 2n Access Region Description EDS LCKS...

Page 699: ...1 0 Slot Assigned Message buffer assigned to next static slot Ready for Null Frame transmission CCSaCCITx 1 0 TX Slot Assigned and Internal Message Transfer Message buffer assigned to next static slo...

Page 700: ...commands can be issued on the commit side only Any lock or unlock command issued on the transmit side will be ignored and the double transmit buffer lock error flag DBL_EF in the CHI Error Flag Regis...

Page 701: ...op transfer of message data from commit side to transmit side Note The internal message transfer is stopped before the slot or segment start transmit side specific transitions SA slot match and static...

Page 702: ...swapping the commit side CMT bit is cleared the commit side interrupt flag MBIF is set the transmit side CMT bit is set and the transmit side DVAL bit is cleared The conditions and the point in time w...

Page 703: ...lled 1 the commit side is in the Idle state 2 the commit site message data are valid i e MBCCSR 2n CMT 1 3 the transmit side is in one of the states Idle CCSa or CCMa It is not checked whether the tra...

Page 704: ...ommit side is locked by the application This is implemented to provide the slot status of the most recent transmission slot 22 6 7 Individual Message Buffer Search This section provides a detailed des...

Page 705: ...mission If the cycle counter filter is disabled i e CCFE 0 this set of cycles consists of all communication cycles If the cycle counter filter of a message buffer does not match a certain communicatio...

Page 706: ...ies to the dynamic segment only and refers to the functionality if there are transmit as well as receive message buffers are configured for the same slot According to Table 22 113 the transmit buffer...

Page 707: ...r Type Not Changed RC2 A reconfiguration will not change the buffer type of the individual message buffer if the message buffer buffer type bit MBCCSRn MBT is not changed This type of reconfiguration...

Page 708: ...memory base address for the FIFO buffers is System Memory Base Address Register SYMBADR 22 6 9 2 2 Dual System Memory Base Address Mode This mode is configured when the FIFO address mode flag MCR FAM...

Page 709: ...rame header into the message buffer header field indicated by the controller internal FIFO write index The frame payload data are written into the corresponding message buffer data field If the status...

Page 710: ...e remaining fl pc requested pop operations are discarded without any notification In this case FIFOA FIFOB is empty after the update operation The read index in the Receive FIFO A Read Index Register...

Page 711: ...ue Frame ID Append to FIFO vRF Frame ID No Frame Received FIFO full Set FIFO Overflow Interrupt Flag Message Buffer Found No Passed Passed Passed Yes vRF Header NFIndicator 0 Mask Rejection Filter Ran...

Page 712: ...s are rejected no frame will pass This is the reset value for the RX FIFO 22 6 9 9 2 RX FIFO Frame ID Range Rejection Filter Each of the four RX FIFO Frame ID Range filters can be configured as a reje...

Page 713: ...payload preamble indicator bit PPI set to 1 and with the message ID MID the first two bytes of the payload will pass the RX FIFO Message ID Acceptance Filter if Equation 22 18 is fulfilled Eqn 22 18 T...

Page 714: ...ernal channel A and the FlexRay Port A is used Depending on the setting of MCR CHA and MCR CHB the internal channel A behaves either as a FlexRay Channel A or FlexRay Channel B The bit MCR CHA must be...

Page 715: ...P fields in the Protocol Operation Control Register POCR The PE applies the external correction values in the next even odd cycle pair as shown in Figure 22 142 and Figure 22 143 CHI PE cfg A reg A cC...

Page 716: ...le 2n 1 If this field is written to after the end of the static segment of cycle 2n 1 it is not guaranteed that the external correction value is applied in cycle pair 2n 2 2n 3 If the value is not app...

Page 717: ...c Frame ID ChA 5 Sync Frame ID ChA 6 Sync Frame ID ChA 7 Sync Frame ID ChA 8 Sync Frame ID ChA 9 Sync Frame ID ChA 10 Sync Frame ID ChA 11 Sync Frame ID ChA 12 Sync Frame ID ChA 13 Sync Frame ID ChA 1...

Page 718: ...n transferred into the flexray memory the controller sets the even table valid bit SFTCCSR EVAL and the Even Cycle Table Written Interrupt Flag EVT_IF in the Protocol Interrupt Flag Register 1 PIFR1 I...

Page 719: ...lexray memory the lock is granted immediately and the lock status bit ELKS OLKS is set If the affected table is currently written to the flexray memory the lock is not granted In this case the applica...

Page 720: ...s assigned and the controller is in POC normal active a frame of the type as shown in Table 22 115 is transmitted If a transmit message buffer is configured for the key slot and a valid message is ava...

Page 721: ...Frame Rejection Filtering The synchronization frame rejection filter is a comparator The compare value is defined by the Sync Frame ID Rejection Filter Register SFIDRFR A received synchronization fram...

Page 722: ...es before the strobe signal is changed These signals are listed in Table 22 12 with a positive clock offset An example waveform is given in Figure 22 147 Figure 22 147 Strobe Signal Timing type pulse...

Page 723: ...he timer expires but is repetitive the T2ST bit is not cleared and the timer is restarted immediately The T2ST is cleared when the timer is stopped 22 6 17 2 1 Absolute Timer T2 If timer T2 is configu...

Page 724: ...NIT on a per channel base The content of the slot status vector is described in Table 22 116 The PE provides the slot status vector within the first macrotick after the end of the related slot window...

Page 725: ...transmission starts for slots in which the module does not transmit vSS TxConflict reception ongoing while transmission starts first valid channel that has received the first valid frame received fra...

Page 726: ...nal slot status counter is incremented if its increment condition defined by the Slot Status Counter Condition Register SSCCR matches the status vector provided by the PE All static slots the symbol w...

Page 727: ...le cycle mode i e SSCCRn MCY 0 the internal slot status counter SSCRn_INT is reset at each cycle start If the slot status counter is in the multicycle mode i e SSCCRn MCY 1 the counter is not reset an...

Page 728: ...ed by all zeros Depending on the point in time this can affect the PPI bit the Header CRC the Payload Length in case of an dynamic slot and the payload data Starting from the next slot in the current...

Page 729: ...n interrupt enable bit 22 6 20 1 5 CHI Error Interrupts The controller provides 16 interrupt sources for CHI related error events For details see CHI Error Flag Register CHIERFR There is one common in...

Page 730: ...request CHIIRQ is generated when at least one of the individual chi error interrupt sources generates an interrupt request and the interrupt enable bit GIFER CHIE is set 22 6 20 2 5 Module Interrupt T...

Page 731: ...als MBCCSRn MBIF n CHIER 15 0 16 PIFR0 15 0 16 PIFR1 15 0 16 RBIRQ CHIIRQ PRTIRQ GIFER FAFAIF FAFAIRQ GIFER WUPIF WUPIRQ GIFER RBIE MBCCSRn MTD Receive Transmit GIFER PRIE GIFER WUPIE GIFER MIE MBCCSR...

Page 732: ...of samples per bit cSamplesPerBit and the strobe offset cStrobeOffset The application configures the FlexRay channel bit rate by setting the BITRATE field in the Module Configuration Register MCR The...

Page 733: ...es the module related initialization steps after a system reset 1 Configure controller a configure the control bits in the Module Configuration Register MCR b configure the system memory base address...

Page 734: ...s MBIDXRn d configure the FIFOs e issue CONFIG_COMPLETE command via Protocol Operation Control Register POCR f wait for POC ready in Protocol Status Register 0 PSR0 After this sequence the controller...

Page 735: ...Eqn 22 32 This results in the formula given in Equation 22 33 which determines the required minimum CHI frequency for a given number of message buffers that are utilized Eqn 22 33 The minimum CHI fre...

Page 736: ...ill be removed from this vector 22 7 5 Message Buffer Search on Simple Message Buffer Configuration This sections describes the message buffer search behavior for a simplified message buffer configura...

Page 737: ...2 is assigned to both buffers Table 22 120 Transmit Buffer Configuration Register Field Value Description MBCCSRt MCM used only for double buffers MBT 0 single transmit buffer MTD 1 transmit buffer MB...

Page 738: ...ment The FlexRay protocol requires When a slot occurs if a slot is assigned to a node on a channel that node only transmits a frame on that channel if there is data ready and there is a match on relev...

Page 739: ...nual Rev 1 b for the cycles in the set 4n 2 which is assigned to the receive buffer only the receive buffer will be found and the node can receive data The receive and transmit cycles are shown in Fig...

Page 740: ...FlexRay Communication Controller FLEXRAY 22 156 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...

Page 741: ...Introduction The eMIOS200 provides functionality to generate or measure time events The eMIOS200 is implemented with its own configuration of timer channels to suit the target applications needs while...

Page 742: ...annel 0 B EMIOS 7 EMIOS 0 A Counter Buses Time Bases All Submodules Internal Counter Clock Enable IIB eMIOS Channel Flags Global Time Base Enable Global Time Base Bit GTBE Output System Clock BIU IP I...

Page 743: ...e timebase of each channel can be started simultaneously Shared time bases through the counter buses Shadow FLAG register State of eMIOS200 can be frozen for debug purposes Debug mode is supported 23...

Page 744: ...se Edge Accumulation PEA 23 4 1 1 7 23 31 Pulse Edge Counting PEC 23 4 1 1 8 23 33 Quadrature Decode QDEC 23 4 1 1 9 23 35 Windowed Programmable Time Accumulation WPTA 23 4 1 1 10 23 36 Modulus Counte...

Page 745: ...s an output the UCOUT bit of the EMIOS_CSR n register reflects the state of the output pin NOTE All eMIOS channels support both input and output functions When the eMIOS function is the primary functi...

Page 746: ...0x0020 EMIOS_CADR 0 Channel A Data Register 32 R W 0x0000_0000 23 3 2 4 23 10 0x0024 EMIOS_CBDR 0 Channel B Data Register 32 R W 0x0000_0000 23 3 2 5 23 11 0x0028 EMIOS_CCNTR 0 Channel Counter Regist...

Page 747: ...ccessed in these modes Table 23 3 Unified Channel Base Offsets Unified Channel Offset from EMIOS_BASE 0xC3FA_0000 Unified Channel Offset from EMIOS_BASE 0xC3FA_0000 Unified Channel 0 0x0020 Unified Ch...

Page 748: ...00 to freeze the registers of the unified channels when debug mode is requested at MCU level Each unified channel must have FREN bit set in order to enter freeze mode While in freeze mode the eMIOS200...

Page 749: ...B TCR1 0010 eTPU engine A TCR2 0011 eTPU engine B TCR2 0100 1111 Reserved 16 23 GPRE Global Prescaler Bits The GPRE bits select the clock divider value for the global prescaler 24 31 Reserved Offset...

Page 750: ...OU28 OU27 OU26 OU25 OU24 OU23 OU22 OU21 OU20 OU19 OU18 OU17 OU16 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R OU15 OU14 OU13 OU12 OU11 OU10 OU9 OU8 OU7 OU...

Page 751: ...s implemented then the register is present Otherwise it is absent PXR40 has register B EMIOS_CBDR in all channels Offset UC n base address 0x0004 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13...

Page 752: ...A1 B2 B1 OPWMCB A2 A1 B2 B1 OPWMB A2 A1 B2 B1 1 In these modes the register EMIOS_CBDR n is not used but B2 can be accessed Offset UC n base address 0x0008 Access User read write 0 1 2 3 4 5 6 7 8 9...

Page 753: ...signal is asserted the output pin goes to EDPOL for OPWFMB and OPWMB modes and to the complement of EDPOL for other modes but the unified channel continues to operate normally i e it continues to pro...

Page 754: ...on comparator A except that the FLAG bit is not set This bit is cleared by reset and is always read as 0 This bit is valid for every output operation mode which uses comparator A otherwise it has no...

Page 755: ...this bit has no effect 0 Single edge triggering defined by the EDPOL bit 1 Both edges triggering For GPIO in mode the EDSEL bit selects if a FLAG can be generated 0 A FLAG is generated as defined by...

Page 756: ...t the logic level on the output pin 0 A match on comparator A clears the output flip flop while a match on comparator B sets it 1 A match on comparator A sets the output flip flop while a match on com...

Page 757: ...update 001_1010 OPWFM Output Pulse Width and Frequency Modulation flag on A or B matches immediate update 001_1011 OPWFM Output Pulse Width and Frequency Modulation flag on A or B matches next period...

Page 758: ...dge trailing edge dead time 101_1101 OPWMCB Center Aligned Output Pulse Width Modulation Buffered flag in trailing edge leading edge dead time 101_1110 OPWMCB Center Aligned Output Pulse Width Modulat...

Page 759: ...has occurred in the internal counter This bit must be cleared by software writing a 1 0 An overflow has not occurred 1 An overflow has occurred 17 28 Reserved 29 UCIN Unified Channel Input Pin Bit The...

Page 760: ...ts of Counter bus selector which selects the time base to be used by the channel for all timing functions A programmable clock prescaler Two double buffered data registers A and B that allow up to two...

Page 761: ...fied channel control block diagram channel_controller ipd_done ipd_req uc_int_flag biu_channel_en n biu_a_en biu_b_en biu_cnt_en Clock Prescaler biu_control_en biu_status_en ips_byte 7 0 ips_byte 15 8...

Page 762: ...neration even if A and B registers are changed on the fly the MCB OPWFMB OPWMB and OPWMCB modes are available In these modes the A and B registers are double buffered These modes are presented in sepa...

Page 763: ...alue on the selected time base is captured into register A2 At the same time the FLAG bit is set to indicate that an input capture has occurred The EMIOS_CADR n register returns the value of register...

Page 764: ...he EMIOS_CCR n register The counter bus can be either internal or external and is selected through the BSL bits Figure 23 15 and Figure 23 16 show how the unified channel can be used to perform a sing...

Page 765: ...x001100 0x001000 0x001100 0x001000 1 EMIOS_CADR n A2 A2 A1 according to OU n bit Update to A1 EDSEL 0 Output Flip Flop EDPOL 1 A1 Value1 0x001000 Selected Counter Bus FLAG Pin Register A1 Match A1 Mat...

Page 766: ...ters EMIOS_CADR n and EMIOS_CBDR n return the value in registers A2 and B1 respectively In order to guarantee coherent access reading EMIOS_CADR n forces B1 to be updated with the content of register...

Page 767: ...d into the registers A2 and B2 and the data previously held in register B2 is transferred to register B1 On this first capture the FLAG line is not set and the values in registers B1 are meaningless O...

Page 768: ...contents of register A1 are transferred to register B1 and the transfers from B2 to B1 are re enabled to occur at the transfer edges which is the leading edge in the Figure 23 21 example Figure 23 21...

Page 769: ...ators A and B are enabled and disabled independently The output flip flop is set to the value of EDPOL when a match occurs on comparator A and to the complement of EDPOL when a match occurs on compara...

Page 770: ...tch 0xxxxxxx 0x001100 0x001100 0x001100 A1 Match Update to A1 B1 Output Flip Flop A1 Value1 B1 Value2 A2 A1 according to OU n bit B2 B1 according to OU n bit 0x000500 0x001000 0x001100 0x001000 0x0011...

Page 771: ...from B2 to B1 These transfers are disabled until the next read of the EMIOS_CBDR n register Reading the EMIOS_CBDR n register re enables transfers from B2 to B1 to take effect at the next transfer ev...

Page 772: ...the counter is cleared on the next input event after a FLAG generation and continues to operate as previously described For single shot operation MODE 6 set MODE 0 6 000_1001 the counter is not cleare...

Page 773: ...he selected time base clears the internal counter and counting is enabled again In order to guarantee coherent measurements when reading EMIOS_CCNTR n after the FLAG is set the software must check if...

Page 774: ...Value2 0x000303 0x000303 0x000303 0x000090 Notes 1 EMIOS_CADR n A1 2 EMIOS_CBDR n B1 MODE 6 0 3 EMIOS_ALTA n A2 A2 Value3 A2 EMIOS_CCNTR n A2 EMIOS_CCNTR n A1 Match A1 B1 B1 Match B1 Match A1 Match Wr...

Page 775: ...be connected to the direction signal and the UC n 1 input pin must be connected to the count signal of the quadrature encoder The EDPOL bit for UC n selects the count direction according to the direct...

Page 776: ...h occurs in comparator B the internal counter is disabled regardless of the input signal polarity and the FLAG bit is set At the same time the contents of the EMIOS_CCNTR n register is transferred to...

Page 777: ...t MODE 001_000b When MODE 6 is set the external clock is selected In this case the internal counter clears as soon as the match signal occurs The channel FLAG bit is set at the same time the match occ...

Page 778: ...MODE 001_01bb a match between the internal counter and register A1 sets the FLAG and changes the counter direction from increment to decrement A match between register B1 and the internal counter chan...

Page 779: ...y the EDPOL and EDSEL bits in the EMIOS_CCR n channel register When entering MCB mode if the up counter is selected by MODE 4 0 the internal counter starts counting up from its current value until the...

Page 780: ...erated only on an A1 match If MODE 5 is set to 1 flags are also generated at the cycle boundary Figure 23 35 MCB Up Down Mode Figure 23 36 shows the A1 register update process in up counter mode The A...

Page 781: ...ng the A1 register update to be delayed for synchronization purposes Figure 23 36 MCB Mode A1 Register Update in Up Counter Mode Figure 23 37 shows the A1 register update in up down counter mode Note...

Page 782: ...mplement of the EDPOL bit and the internal counter is cleared FLAG can be generated at match B when MODE 5 is cleared or in both matches when MODE 5 is set At any time the FORCMA and FORCMB bits allow...

Page 783: ...when changing the registers values on the fly This mode supports 0 and 100 duty cycles 0x001000 0x000000 Time Output Flip Flop A1 Value1 B1 Value B2 Value2 0x000900 0x000900 0x001000 0x001000 0x000200...

Page 784: ...s entered When a match on comparator A occurs the output register is set to the value of EDPOL When a match on comparator B occurs the output register is set to the complement of EDPOL B1 match also c...

Page 785: ...ed as the cycle boundary The load signal pulse has the duration of one system clock period If A2 and B2 are written within cycle n their values are loaded into A1 and B1 respectively at the first cloc...

Page 786: ...applications that use active high signals and a high to low transition at A1 match In this case EDPOL should be set to 0 Note that both the channel and global prescalers are set to 0x00_0000 each divi...

Page 787: ...a match on comparators A or B respectively Similar to a B1 match FORCMB sets the internal counter to 0x00_0001 The FLAG bit is not set by the FORCMA or FORCMB bits being asserted Figure 23 44 shows th...

Page 788: ...e insertion the output PWM duty cycle is equal to the sum of register A1 and register B1 Mode 6 bit selects between trailing and leading dead time insertion NOTE The internal counter may be running in...

Page 789: ...he FORCMA or FORCMB bits only allow the software to force the output flip flop to the level corresponding of a match on A or B respectively If subsequent matches occur on comparators A and B the PWM p...

Page 790: ...000200 0x000000 Internal Counter Time 0x000010 0x000010 B1 Value2 A2 A1 according to OU n bit B2 B1 according to OU n bit MODE 0 1 Match A1 Update B1 Match B1 Match B1 Match A1 Match A1 Match A1 Updat...

Page 791: ...rtion the output PWM duty cycle is equal to the sum of register A1 and register B1 Mode 6 selects between trailing and leading dead time insertion NOTE The internal counter runs in the internal presca...

Page 792: ...and the internal time base the output flip flop is set to the value of the EDPOL bit In the following match between register A1 and the selected time base the output flip flop is set to the complement...

Page 793: ...A1 and the selected time base the internal counter is set to 0x00_0001 and B1 matches are enabled When the match between register B1 and the selected time base occurs the output flip flop is set to th...

Page 794: ...ding or trail In leading dead time insertion FORCMA forces a transition in the output flip flop to the opposite of the EDPOL bit In trailing dead time insertion the output flip flop is forced to the v...

Page 795: ...bus period then a 0 duty cycle is produced only if the pin starts the current cycle in the opposite of the EDPOL value In case of 100 duty cycle the transition from EDPOL to the opposite of EDPOL may...

Page 796: ...he delay from matches to output flip flop transition in OPWFMB mode The operation of OPWMCB mode is similar to OPWFMB regarding matches and output pin transition 23 4 1 1 17 Output Pulse Width Modulat...

Page 797: ...e output flip flop is set at every period to the value of EDPOL bit 0 duty cycle is possible by writing 0x0 to register A EMIOS_CADR When a match occurs the output flip flop is set at every period to...

Page 798: ...hes when MODE 5 is cleared or in both A1 and B1 matches when MODE 5 is set If subsequent matches occur on comparators A and B the PWM pulses continue to be generated regardless of the state of the FLA...

Page 799: ...the value of the A1 register being set to 0 In this case the match positive edge is used instead of the negative edge to transition the output flip flop Figure 23 54 shows the channel operation for 0...

Page 800: ...A1 or B1 match The output disable does not modify the flag bit behavior There is a delay of one system clock between the assertion of the output disable signal and the transition of the output pin to...

Page 801: ...ite of EDPOL bit at B1 match If B1 is set to 0x00_0009 for instance B1 match does not occur thus a 0 duty cycle signal is generated Cycle n Cycle n 1 Cycle n 2 A1 Value B1 Value B2 Value 0x000008 0x00...

Page 802: ...ow the counter is reset At the next pin transition the counter starts counting again Any pulse that is shorter than a full range of the masked counter is regarded as a glitch and it is not passed on t...

Page 803: ...sired level During input modes any input events that may occur while the channel is frozen are ignored When exiting debug mode or when the freeze enable bit is cleared FRZ in the EMIOS_MCR or FREN in...

Page 804: ...m EMIOS_MCR SRV bits select the time slot of the STAC output bus Figure 23 60 shows a timing diagram for the STAC client submodule Figure 23 60 Timing Diagram for the STAC Bus and STAC Client Submodul...

Page 805: ...d glitches the following steps must be performed whenever any update in the prescaling rate is desired 1 Write 0 at GPREN bit in EMIOSMCR register thus disabling global prescaler 2 Write the desired v...

Page 806: ...e routine 23 7 2 Application Information Correlated output signals can be generated by all output operation modes The OU n bits in EMIOS_OUDR can be used to control the update of these output signals...

Page 807: ...igure 23 65 If OPWFM mode is selected the internal counter behaves as described in Figure 23 64 The internal counter clears at the start of the match signal skips the next prescaled clock edge and the...

Page 808: ...0 FLAG Set Event FLAG Clear FLAG Pin Register of prescaler clock enable the counter will start counting System Clock Prescaler Clock Enable Internal Counter Match Value 3 0 1 3 0 2 0 3 0 PRESCALED CL...

Page 809: ...n registers to get a new measurement The FLAG indicates that new data has been captured and it is the only way to assure data coherency The FLAG set event can be detected by polling the FLAG bit or b...

Page 810: ...Enhanced Modular Input Output Subsystem eMIOS200 23 70 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...

Page 811: ...on controller implementing the CAN protocol according to the CAN 2 0B protocol specification Ref 1 A general block diagram is shown in Figure 24 1 which describes the main sub blocks implemented in th...

Page 812: ...e CAN protocol specification Version 2 0 B Ref 1 which supports both standard and extended message frames A flexible number of Message Buffers 16 32 or 64 is also supported The Message Buffers are sto...

Page 813: ...Flexible Message Buffers 64 of zero to eight bytes data length Each MB configurable as Rx or Tx all supporting standard and extended messages Individual Rx Mask Registers per Message Buffer Includes...

Page 814: ...edged it will flag a BIT0 error without changing the REC as if it was trying to acknowledge the message Loop Back Mode The module enters this mode when the LPB bit in the Control Register is asserted...

Page 815: ...U The addresses presented here are relative to the base address The address space occupied by FlexCAN has 96 bytes for registers starting at the module base address followed by MB storage space in emb...

Page 816: ...M 1056 and 256 bytes respectively only when FlexCAN is configured with 64 MBs When it is configured with 16 MBs the memory sizes are 288 and 64 bytes so the address ranges 0x0180 0x047F and 0x08C0 0x0...

Page 817: ...unter Register 32 S 0x0000_0000 Yes Yes 24 3 4 7 23 Base 0x0020 FLEXCAN_x_ESR Error and Status Register 32 S 0x0000_0000 Yes Yes 24 3 4 8 25 Base 0x0024 FLEXCAN_x_IMASK2 Interrupt Masks 2 32 S 0x0000_...

Page 818: ...th Extended and Standard Frames 29 bit Identifier and 11 bit Identifier respectively used in the CAN specification Version 2 0 Part B are represented NOTES 1 FLEXCAN_A 0xFFFC_0000 FLEXCAN_B 0xFFFC_400...

Page 819: ...considered as a successful bit transmission 0 Indicates the current MB has a Data Frame to be transmitted 1 Indicates the current MB has a Remote Frame to be transmitted LENGTH Length of Data in Byte...

Page 820: ...ode indicates OVERRUN but the CPU reads the C S word and then unlocks the MB when a new frame is written to the MB the code returns to FULL 0110 If the code already indicates OVERRUN and yet another n...

Page 821: ...is allowed to participate in the current arbitration process and the Code field is automatically updated to 1110 to allow the MB to participate in future arbitration runs When the frame is eventually...

Page 822: ...an 8 entry ID table that specifies filtering criteria for accepting frames into the FIFO Figure 24 4 shows the three different formats that the elements of the ID table can assume depending on the IDA...

Page 823: ...y match the target ID 0 Extended frames are rejected and standard frames can be accepted 1 Extended frames can be accepted and standard frames are rejected RXIDA Rx Frame Identifier Format A Specifies...

Page 824: ..._x_MCR Field Descriptions Field Description 0 MDIS Module Disable This bit controls whether FlexCAN is enabled or not When disabled FlexCAN shuts down the clocks to the CAN Protocol Interface and Mess...

Page 825: ...FLEXCAN_x_RXGMASK FLEXCAN_x_RX14MASK FLEXCAN_x_RX15MASK all Message Buffers The SOFT_RST bit can be asserted directly by the CPU when it writes to the FLEXCAN_x_MCR Register but it is also asserted wh...

Page 826: ...modes 1 FlexCAN is either in Disable Mode or Stop mode 12 Reserved 13 DOZE Doze Mode Enable Doze Mode is not supported on this device Leave this bit as 0 0 FlexCAN is not enabled to enter low power mo...

Page 827: ...bit field identifies the format of the elements of the Rx FIFO filter table as shown in Table 24 9 Note that all elements of the table are configured at the same time by this field they are all the sa...

Page 828: ...escriptions Field Description 0 7 PRESDIV Prescaler Division Factor This 8 bit field defines the ratio between the CPI clock frequency and the Serial Clock Sclock frequency The Sclock period defines t...

Page 829: ...for the Rx Warning Interrupt associated with the RWRN_INT flag in the Error and Status Register This bit has no effect if the WRN_EN bit in FLEXCAN_x_MCR is negated and it is read as zero when WRN_EN...

Page 830: ...ch time a message is received in Message Buffer 0 This feature provides means to synchronize multiple FlexCAN stations with a special SYNC message i e global network time If the FEN bit in FLEXCAN_x_M...

Page 831: ...ning of the identifier field of any frame on the CAN bus This captured value is written into the Time Stamp entry in a message buffer after a successful reception or transmission of a message Writing...

Page 832: ...operation FLEXCAN_x_RX14MASK is used as acceptance mask for the Identifier in Message Buffer 14 When the FEN bit in FLEXCAN_x_MCR is set FIFO enabled the RXG14MASK also applies to element 6 of the ID...

Page 833: ...t that the data will take some time to be actually written to the register If desired software can poll the register to discover when the data was actually written FlexCAN responds to any bus state as...

Page 834: ..._Err_Counter does not increment anymore by acknowledge errors Therefore the device never goes to the Bus Off state If the Rx_Err_Counter increases to a value greater than 127 it is not incremented fur...

Page 835: ...us bits Most bits in this register are read only except TWRN_INT RWRN_INT BOFF_INT and ERR_INT that are interrupt flags that can be cleared by writing 1 to them writing 0 has no effect See Section 24...

Page 836: ...as dominant Note This bit is not set by a transmitter in case of arbitration field or ACK slot or in case of a node sending a passive error flag that detects dominant bits 17 BIT0_ERR Bit0 Error This...

Page 837: ...r is asserted the FLT_CONF field will indicate Error Passive Since the Control Register is not affected by soft reset the FLT_CONF field will not be affected by soft reset if the LOM bit is asserted 0...

Page 838: ...9M BUF 58M BUF 57M BUF 56M BUF 55M BUF 54M BUF 53M BUF 52M BUF 51M BUF 50M BUF 49M BUF 48M W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R BUF 47M BUF 46M BUF...

Page 839: ...bit enables or disables the respective FlexCAN Message Buffer MB0 to MB31 Interrupt 0 The corresponding buffer Interrupt is disabled 1 The corresponding buffer Interrupt is enabled Note Setting or cle...

Page 840: ...d the function of the 8 least significant interrupt flags BUF7I BUF0I is changed to support the FIFO operation BUF7I BUF6I and BUF5I indicate operating conditions of the FIFO while BUF4I to BUF0I are...

Page 841: ...cupied FIFO almost full 0 No such occurrence 1 MB6 completed transmission reception or FIFO almost full 26 BUF5I Buffer MB5 Interrupt or Frames available in FIFO If the FIFO is not enabled this bit fl...

Page 842: ...mes The mailbox system is composed by a set of 64 Message Buffers MB that store configuration and control data time stamp message ID and data see Section 24 3 2 Message Buffer Structure The memory cor...

Page 843: ...process and eventually be transmitted according to its priority At the end of the successful transmission the value of the Free Running Timer is written into the Time Stamp field the Code field in the...

Page 844: ...nding MB is blocked if the AEN bit in FLEXCAN_x_MCR is asserted The write access is released in the following events After the MB is transmitted FlexCAN enters in HALT or BUS OFF FlexCAN loses the bus...

Page 845: ...Registers and not by the Code field of that MB Polling the Code field does not work because once a frame was received and the CPU services the MB by reading the C S word followed by unlocking the MB...

Page 846: ...the matching algorithm keeps looking for another free MB until it finds one If it can not find one that is free then it will overwrite the last matching MB unless it is locked and set the Code field t...

Page 847: ...back mechanism is provided to inform the CPU if the transmission was aborted or if the frame could not be aborted and was transmitted instead In order to maintain backwards compatibility the abort mec...

Page 848: ...only for the current match arbitration round The purpose of deactivation is data coherency The match arbitration process scans the MBs to decide which MB to transmit or receive If the CPU updates the...

Page 849: ...finds out that there are no free to receive MBs so it decides to override MB number 5 However this MB is locked so the new message can not be written there It will remain in the SMB waiting for the MB...

Page 850: ...intended for the target application thus reducing the interrupt servicing work load The filtering criteria is specified by programming a table of 8 32 bit registers that can be configured to one of t...

Page 851: ...ely enters the internal arbitration process but is considered as normal Tx MB with no higher priority The data length of this frame is independent of the DLC field in the remote frame that initiated i...

Page 852: ...oscillator Oscillator Clock or to the Peripheral system Clock from PLL In order to guarantee reliable operation the clock source should be selected while the module is in Disable Mode bit MDIS set in...

Page 853: ...s within the Bit Time Table 24 20 gives an overview of the CAN compliant segment settings and the related parameter values 1 For further explanation of the underlying concepts please refer to ISO DIS...

Page 854: ...tching and arbitration FlexCAN needs to scan the whole Message Buffer memory during the available time slot In order to have sufficient time to do that the following requirements must be observed A va...

Page 855: ...necessary that the FRZ bit is asserted in the FLEXCAN_x_MCR Register and the module is not in any of the low power modes Disable Stop When Freeze Mode is requested during transmission or reception Fl...

Page 856: ...is a system low power mode in which all MCU clocks are stopped for maximum power savings If FlexCAN receives the global Stop Mode request during Freeze Mode it sets the MDISACK bit negates the FRZ_ACK...

Page 857: ...e the MB ones and can be read from the Error and Status Register The Bus Off Error Tx Warning and Rx Warning interrupt mask bits are located in the Control Register 24 4 11 Bus Interface The CPU acces...

Page 858: ...is selected and the module is enabled MDIS bit negated FlexCAN automatically goes to Freeze Mode In Freeze Mode FlexCAN is un synchronized to the CAN bus the HALT and FRZ bits in FLEXCAN_x_MCR Registe...

Page 859: ...th the last event FlexCAN attempts to synchronize to the CAN bus 24 5 2 FlexCAN Addressing and RAM size configurations There are 3 RAM configurations that can be implemented within the FlexCAN module...

Page 860: ...FlexCAN Module 24 50 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...

Page 861: ...ck Diagram NOTE The TXSS signal is described on Section 25 3 2 1 DSPI Module Configuration Register DSPI_MCR For details on 32 bits operation see Section 25 4 9 Timed Serial Bus TSB CMD DMA and interr...

Page 862: ...uest submodule of the SIU Combined Serial Interface CSI Configuration where the DSPI operates in both SPI and DSI configurations interleaving DSI frames with SPI frames giving priority to SPI frames F...

Page 863: ...of current frame complete TCF Attempt to transmit with an empty Transmit FIFO TFUF RX FIFO is not empty RFDF Frame received while Receive FIFO is full RFOF Modified SPI transfer formats for communicat...

Page 864: ...DSPI to operate as a basic SPI block with the FIFOs providing support for external queue operation Data to be transmitted and data received reside in separate FIFOs The FIFOs can be popped and pushed...

Page 865: ...to a register The MCU specific modes are controlled by signals external to the DSPI The MCU specific modes are modes that the entire MCU may enter in parallel to the DSPI being in one of its block sp...

Page 866: ...nded for In Slave Mode the SS signal is a Slave Select input signal that allows a SPI master to select the DSPI as the target for transmission 25 2 2 2 PCS 1 PCS 3 Peripheral Chip Selects 1 3 PCS 1 PC...

Page 867: ...intended for PCSS provides a strobe signal that can be used with an external demultiplexer for deglitching of the PCS signals When the DSPI is in Master Mode and the PCSSE bit in the DSPI_MCR is set t...

Page 868: ...BASE 0x28 DSPI_CTAR0 DSPI Clock and Transfer Attributes Register 0 DSPI_CTAR7 DSPI Clock and Transfer Attributes Register 7 32 R W 0x7800_0000 25 3 2 3 12 DSPI_BASE 0x2C DSPI_SR DSPI Status Register 3...

Page 869: ...ansmit Comparison Register 32 R 0x0000_0000 25 3 2 13 29 DSPI_BASE 0xCC DSPI_DDR DSPI DSI Deserialization Data Register 32 R 0x0000_0000 25 3 2 14 29 DSPI_BASE 0xD0 DSPI_DSICR1 DSPI DSI TSB Configurat...

Page 870: ...PCSSE Peripheral Chip Select Strobe Enable The PCSSE bit enables the PCS 5 PCSS to operate as an PCS Strobe output signal See Section 25 4 6 5 Peripheral Chip Select Strobe Enable PCSS for more infor...

Page 871: ...O is disabled the receive part of the DSPI operates as a simplified double buffered SPI See Section 25 4 3 3 FIFO Disable Operation for details 0 RX FIFO is enabled 1 RX FIFO is disabled 20 CLR_TXF Cl...

Page 872: ...tion Register DSPI_DSICR selects which of the DSPI_CTAR register is used When the DSPI is configured as a DSI bus Slave the DSPI_CTAR1 register is used In CSI Configuration the transfer attributes are...

Page 873: ...ly tDT is supported for TSB However in TSB non continuous clock mode both the PDT and DT delays are valid Address DSPI_BASE 0xC DSPI_BASE 0x28 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R DBR FM...

Page 874: ...point regardless of how many bits are remaining will be controlled by the DSPI_DSICR1 register 5 CPOL Clock Polarity The CPOL bit selects the inactive state of the Serial Communications Clock SCK Thi...

Page 875: ...ame The PDT field is only used in Master Mode The table below lists the prescaler values See the DT 0 3 field description for details on how to compute the Delay after Transfer 14 15 PBR Baud Rate Pre...

Page 876: ...ter Mode The Delay after Transfer is the time between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame Table 25 12 lists the scaler valu...

Page 877: ...101 14 0110 7 1110 15 0111 8 1111 16 Table 25 10 DSPI PCS to SCK Delay Scaler CSSCK PCS to SCK Delay Scaler Value CSSCK PCS to SCK Delay Scaler Value 0000 2 1000 512 0001 4 1001 1024 0010 8 1010 2048...

Page 878: ...ing mechanisms 0100 32 1100 8192 0101 64 1101 16384 0110 128 1110 32768 0111 256 1111 65536 Table 25 12 DSPI Delay after Transfer Scaler DT Delay after Transfer Scaler Value DT Delay after Transfer Sc...

Page 879: ...f Queue Flag The EOQF bit indicates that transmission in progress is the last entry in a queue The EOQF bit is set when TX FIFO entry has the EOQ bit set in the command halfword and the end of the tra...

Page 880: ...edgement from the DMA controller when the RX FIFO is empty 0 RX FIFO is empty 1 RX FIFO is not empty 15 Reserved should be cleared 16 20 TXCTR TX FIFO Counter The TXCTR field indicates the number of v...

Page 881: ...SPI_SR to generate an interrupt request 0 EOQF interrupt requests are disabled 1 EOQF interrupt requests are enabled 4 TFUF_RE Transmit FIFO Underflow Request Enable The TFUF_RE bit enables the TFUF f...

Page 882: ...quest The RFDF_DIRS bit selects between generating an interrupt request or a DMA request 0 RFDF interrupt requests or DMA requests are disabled 1 RFDF interrupt requests or DMA requests are enabled 15...

Page 883: ...PI Master Mode In SPI Slave Mode DSPI_CTAR0 is used The table below shows how the CTAS values map to the DSPI_CTAR registers The number of DSPI_CTAR registers is implementation specific 4 EOQ End Of Q...

Page 884: ...6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R RXDATA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Fig...

Page 885: ...DSICR while the DSPI is in the Running state Table 25 18 DSPI_TXFRn Field Descriptions Field Description 0 15 TXCMD Transmit Command The TXCMD field contains the command that sets the transfer attribu...

Page 886: ...l be one more than the value in the MTOCNT field The number of SCK cycles defined by MTOCNT must be equal to or greater than the frame size When TSBC is set MTOCNT is not used and its value is ignored...

Page 887: ...ntrol for more information When TSBC bit is set CID bit is used for both DSICR and DSICR1 registers 16 DCONT DSI Continuous Peripheral Chip Select Enable The DCONT bit enables the PCS signals to remai...

Page 888: ...only used when TSB is enabled For non TSB configurations only the least 16 significant bits are used Address DSPI_BASE 0xC0 Access Read Only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R SER_DATA W Reset 0...

Page 889: ...I_DDR register holds the signal states for the Parallel Output signals The DSPI_DDR is read only and it is memory mapped so that host software can read the incoming DSI frames Table 25 22 DSPI_ASDR Fi...

Page 890: ...zation Data Register DSPI_DDR Table 25 24 DSPI_DDR Field Descriptions Field Descriptions 0 15 DESER_DAT A Deserialized Data When TSB configuration is set the DESER_DATA field holds deserialized data w...

Page 891: ...ta Select Enable1 When TBSC bit is set the DSE1 bit controls insertion of the zero bit Data Select in the middle of the data frame The insertion bit position is defined by FMSZ field of DSPI_CTARn reg...

Page 892: ...DSPI_CTAR0 DSPI_CTAR7 for information on the fields of the DSPI_CTAR registers The 16 bit shift register in the Master and the 16 bit shift register in the Slave are linked by the SOUT and SIN signals...

Page 893: ...ee Section 25 4 3 Serial Peripheral Interface SPI Configuration for more details In DSI Configuration Master Mode transfer attributes are controlled by the DSPI DSI Configuration Register DSPI_DSICR T...

Page 894: ...t off The DSPI exits External Stop Mode and resumes normal operation once the clocks are turned on Serial communications or register accesses made while in External Stop Mode are ignored even if the c...

Page 895: ...FIFO buffer operations are described in Section 25 4 3 4 Transmit First In First Out TX FIFO Buffering Mechanism and Section 25 4 3 5 Receive First In First Out RX FIFO Buffering Mechanism The interru...

Page 896: ...the TX FIFO or RX FIFO The DSPI operates as a double buffered simplified SPI when the FIFOs are disabled The TX and RX FIFOs are disabled separately The TX FIFO is disabled by writing a 1 to the DIS_T...

Page 897: ...d of a transfer the TCF bit in the DSPI_SR is set to indicate the completion of a transfer The TX FIFO is flushed by writing a 1 to the CLR_TXF bit in DSPI_MCR If an external bus master initiates a tr...

Page 898: ...is empty and the DMA controller indicates that a read from DSPI_POPR is complete or by host software writing a 1 to the RFDF 25 4 4 Deserial Serial Interface DSI Configuration The DSI Configuration su...

Page 899: ...ded to support chaining of several DSPI Details about the MTRIG signal is found in Section 25 4 4 6 Multiple Transfer Operation MTO 25 4 4 3 DSI Serialization In the DSI Configuration from four to six...

Page 900: ...ed on the baud rate at which data is transferred between the DSPI and the external device The baud rate is set in the DSPI_CTAR register selected by the DSICTAS field in the DSPI_DSICR A new DSI frame...

Page 901: ...bled by setting the MTOE bit in the DSPI_DSICR In parallel and serial chaining there is one bus master and multiple bus slaves The bus master initiates and controls the transfers but the DSPI slaves g...

Page 902: ...MTRIG signal to the master DSPI which initiates the transfer When a DSPI slave has its HT signal asserted it also generates a pulse on its MTRIG signal thereby propagating trigger signals from other...

Page 903: ...DSPI slaves For example if one 16 bit DSI frame is created by concatenating eight bits from the DSPI master and four bits from each of the DSPI slaves in Figure 25 23 the DSPI master s frame size must...

Page 904: ...in the figure as PCSx and PCSy The CSI Configuration is only supported in Master Mode Data returned from the external slave while a DSI frame is transferred is placed on the Parallel Output signals D...

Page 905: ...asserts the appropriate CS signal 25 4 5 2 CSI Deserialization The deserialized frames in CSI Configuration goes into the DSPI_SDR or the RX FIFO based on the transfer priority logic When DSI frames a...

Page 906: ...sertion of the PCS signal to the first SCK edge See Figure 25 29 for an illustration of the PCS to SCK delay The PCSSCK and CSSCK fields in the DSPI_CTARx registers select the PCS to SCK delay by the...

Page 907: ...eriod When in TSB and continuous mode the delay is programmed as outlined in the DSPI_CTARx registers but in the event that the delay does not coincide with an SCK period in duration the delay is exte...

Page 908: ...based on the following formula Eqn 25 5 At the end of the transfer the delay between PCSS negation and PCS negation is selected by the PASC field in the DSPI_CTAR based on the following formula Eqn 25...

Page 909: ...e DSPI supports four different transfer formats Classic SPI with CPHA 0 Classic SPI with CPHA 1 Modified Transfer format with CPHA 0 Modified Transfer format with CPHA 1 A modified transfer format is...

Page 910: ...es the data on their SOUT pins on the even numbered clock edges After the last clock edge occurs a delay of tASC is inserted before the master negates the PCS signals A delay of tDT is inserted before...

Page 911: ...frame transfer can be initiated by the master 25 4 7 3 Modified SPI DSI Transfer Format MTFE 1 CPHA 0 In this Modified Transfer Format both the Master and the Slave sample later in the SCK period than...

Page 912: ...25 4 7 4 Modified SPI DSI Transfer Format MTFE 1 CPHA 1 Figure 25 32 shows the Modified Transfer Format for CPHA 1 Only the condition where CPOL 0 is described At the start of a transfer the DSPI ass...

Page 913: ...PI Configuration by setting the CONT bit in the SPI command Continuous Selection is enabled for the DSI Configuration by setting the DCONT bit in the DSPI_DSICR The behavior of the PCS signals in the...

Page 914: ...ith CPHA 1 and CONT 1 Figure 25 34 Example of Continuous Transfer CPHA 1 CONT 1 Switching CTAR registers or changing which PCS signals are asserted between frames while using Continuous Selection can...

Page 915: ...each SPI frame transfer the CTAR specified by the CTAS for the frame shall be used When the DSPI is in DSI configuration the CTAR specified by the DSICTAS field shall be used at all times When the DS...

Page 916: ...it set but no data in the transmit FIFO Continuous SCK with CONT bit set and entering STOPPED state refer to Section 25 4 2 Start and Stop of DSPI Transfers Continuous SCK with CONT bit set and enteri...

Page 917: ...the DSPI DSI Serialization Data Register DSPI_SDR Figure 25 37 DSPI usage in the TSB Configuration The same constraints applied to DSI are valid to TSB but the frame size and the Delay After Transfer...

Page 918: ...occurs is contained in the DSICR register In order to maximize both the setup and hold time margins on the old and new PCS signals the timing of the switch over occurs on the active edge of the maste...

Page 919: ...ys be fixed to a minimum of 1x TSCK 25 4 9 3 TSB Data Frame Format A data frame is transmitted from the TSB controller to the receiving devices Figure 25 40 details the frame active and passive phase...

Page 920: ...errupt Request The End of Queue Request indicates that the end of a transmit queue is reached The End of Queue Request is generated when the EOQ bit in the executing SPI command is asserted and the EO...

Page 921: ...FIFO Drain Request is generated when the number of entries in the RX FIFO is not zero and the RFDF_RE bit in the DSPI_RSER is asserted The RFDF_DIRS bit in the DSPI_RSER selects whether a DMA request...

Page 922: ...initiate the Module Disable Mode by writing a 1 to the MDIS bit in the DSPI_MCR The Module Disable Mode can also be initiated by hardware A power management block can initiate Module Disable Mode by...

Page 923: ...rom a queue is executed The EOQ bit in the command word is set to indicate to the DSPI that this is the last entry in the queue 2 At the end of the transfer corresponding to the command word with EOQ...

Page 924: ...generated based on the prescaler values and the scaler values set in the DSPI_CTAR registers The values calculated assume a 100 MHz system frequency This table does not apply for TSB Continuous Mode...

Page 925: ...O is chosen for the illustration but the concepts carry over to the RX FIFO See Section 25 4 3 4 Transmit First In First Out TX FIFO Buffering Mechanism and Section 25 4 3 5 Receive First In First Out...

Page 926: ...FIFO depth implementation specific 25 5 4 2 Address Calculation for the First in Entry and Last in Entry in the RX FIFO The memory address of the first in entry in the RX FIFO is computed by the foll...

Page 927: ...rial Peripheral Interface DSPI Freescale Semiconductor 25 67 PXR40 Microcontroller Reference Manual Rev 1 RXCTR RX FIFO counter POPNXTPTR Pop Next Pointer RX FIFO Depth Receive FIFO depth implementati...

Page 928: ...Deserial Serial Peripheral Interface DSPI 25 68 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...

Page 929: ...26 1 contains acronyms and abbreviations used in this document 26 1 3 Glossary Table 26 1 Acronyms and Abbreviations Term Description eSCI Enhanced SCI block with LIN support and DMA support SCI Seri...

Page 930: ...to logic level one Preamble The term preamble describes an idle character which is transmitted by the eSCI module Bit time Duration of a single bit in a transmitted byte field or character equivalent...

Page 931: ...king Programmable even or odd parity Programmable polarity of RXD pin Separately enabled transmitter and receiver Two receiver wake up methods Idle line wake up Address mark wake up Interrupt driven o...

Page 932: ...keup characters Programmable wakeup delimiter time Programmable slave timeout Can be configured to include header bits in checksum LIN DMA interface 26 1 6 Modes of Operation The eSCI module has two f...

Page 933: ...s a shut down of the transmit process Therefore it continues the ongoing frame or character transmission until the last bit of the SCI frame or character has been transmitted After the end of the tran...

Page 934: ...bet set No data will be transmitted as long as new LIN frame header data provided by the application If the receiver is still enabled it starts the detection of the start bit 26 2 External Signal Desc...

Page 935: ...egister 2 eSCI_LCR2 0x0010 LIN Transmit Register eSCI_LTR Reserved 0x0014 LIN Receive Register eSCI_LRR Reserved 0x0018 LIN CRC Polynomial Register eSCI_LPR Control Register 3 eSCI_CR3 0x001C Reserved...

Page 936: ...upper byte A word write access to this register updates both the lower and upper byte immediately and is the recommended write access type for this register 26 3 2 2 Control Register 1 eSCI_CR1 This r...

Page 937: ...PE Parity Enable This control bit enables the parity bit generation and checking The location of the parity bits is shown in Section 26 4 2 Frame Formats 0 Parity bit generation and checking disabled...

Page 938: ...transmitted Note This bit should be set in SCI mode only Table 26 7 Receive Source Mode Selection LOOPS RSCR Receiver Input Mode 0 0 Dual Wire Mode 0 1 Reserved 1 0 Loop Mode 1 1 Single Wire Mode eSCI...

Page 939: ...XD pin is not used as output 1 TXD pin is used as output Note This bit is used in Single Wire Mode only BESM Fast Bit Error Detection Sample Mode This bit defines the sample point for the Fast Bit Err...

Page 940: ...terrupt request generation 0 PF interrupt request generation disabled 1 PF interrupt request generation enabled eSCI_BASE 0x0006 Write Anytime 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R RN TN ERR 0 RD 11...

Page 941: ...Tx is shown in bit Rx TD 6 0 Transmit bits 6 to 0 Value of bit Tx is transmitted in BITx eSCI_BASE 0x0008 Write Anytime 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R TDRE TC RDRF IDLE OR NF FE PF BERR TACT...

Page 942: ...ng error during the reception of that frame as described in Section 26 4 5 3 18 Stop Bit Verification PF Parity Error Interrupt Flag This interrupt flag is set when the payload data of a received fram...

Page 943: ...escription is given in Section 26 4 6 5 5 Slave Not Responding Error Detection PBERR Physical Bus Error Interrupt Flag This interrupt flag is set when the receiver input remains unchanged for at least...

Page 944: ...generation disabled 1 RXRDY interrupt request generation enabled TXIE Transmit Data Ready Interrupt Enable This bit controls the eSCI_IFSR2 TXRDY interrupt request generation 0 TXRDY interrupt reques...

Page 945: ...0 0 0 0 0 0 Figure 26 9 LIN Control Register 2 eSCI_LCR2 Table 26 13 eSCI_LCR2 Field Descriptions Field Description UQIE Unrequested Data Received Interrupt Enable This bit controls the eSCI_IFSR2 UR...

Page 946: ...atic identifier parity generation is disabled i e the PRTY bit in LIN Control Register 1 eSCI_LCR1 is 0 ID Identifier This field is used for the identifier field in the protected identifier LEN Frame...

Page 947: ...LRR Field Descriptions Field Description D Receive Data This field provides the data bytes of received LIN RX frames eSCI_BASE 0x0018 Write Anytime 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R P W Reset 1...

Page 948: ...SCI_DR ERR flag not affected by overrun detection 1 ESCI_DR ERR flag is set on overrun detection during frame reception 2 ERFE ERR flag frame error enable 0 ESCI_DR ERR flag not affected by frame erro...

Page 949: ...nd idle characters 26 4 2 1 Data Frame Formats Each data frame contains a character that is surrounded by a start bit an optional parity or address bit and one or two stop bits The supported data fram...

Page 950: ...rmats 2 stop bits Table 26 19 Supported Data Frame Formats for RX only Control Frame Content eSCI_CR3 eSCI_CR1 Start Bits Payload Bits Stop Bits M2 M PE WAKE Character Bits Address Bits Parity Bits SC...

Page 951: ...re and content of the LIN break symbols is shown in Figure 26 20 Figure 26 20 LIN Break Symbol Format The structure and content of the SCI break characters is shown in Figure 26 21 Table 26 20 Support...

Page 952: ...RR determines the module clock divisor The baud rate clock is synchronized with the bus clock and drives the receiver The baud rate clock divided by 16 drives the transmitter The receiver has an acqui...

Page 953: ...ator The baud rate generator is controlled by the value of the SBR field in the Baud Rate Register eSCI_BRR The frequency of the transmitter clock is determined by Equation 26 1 and defines the length...

Page 954: ...a logic zero 26 4 4 1 Faster Receiver Tolerance In this case the receiver has a higher baud rate than the transmitter thus the stop bit sampling starts already in the last transmitted payload bit To e...

Page 955: ...be calculated with the assumption that RS11 is sampled in the transmitted start bit and RS10 is sampled in the last stop bit For an frame with n payload bits and s stop bits the transmitter starts th...

Page 956: ...ct frame format Control Register 1 eSCI_CR1 M Control Register 1 eSCI_CR1 PE Control Register 1 eSCI_CR1 WAKE Control Register 3 eSCI_CR3 M2 select parity type Control Register 1 eSCI_CR1 PT 26 4 5 2...

Page 957: ...are triggered when the described condition or event occurs The send break bit SBK in the Control Register 1 eSCI_CR1 is check for the start condition The internal commit bit iCMT the transmitter acti...

Page 958: ...nfigured and the configured number of stop bits When the last stop bit has been transmitted and the application has not disabled the transmitter the transmitter returns to the Ready state via the done...

Page 959: ...fore entering this mode the application should perform the following actions 1 Configure the module for SCI mode 2 Enable the transmitter by setting TE in Control Register 1 eSCI_CR1 to 1 3 Setup the...

Page 960: ...e transmitter the transmitter continues to transmit the current break character and after it has finished the transmission of this break character it transmits a stop bit The stop bit at the end of a...

Page 961: ...he receiver is changed as shown in Figure 26 27 and the action given in Table 26 30 is executed The module transition shown in Table 26 31 are triggered when the described event occurs Table 26 29 Rec...

Page 962: ...Wire Mode 26 4 5 3 4 Single Wire Mode In Single Wire Mode the RXD pin is disconnected from the eSCI module and the TXD pin is used for both receiving and transmitting Figure 26 29 Single Wire Mode Tab...

Page 963: ...o the received 0 at the stop bit location the reception of a break character causes at least a framing error The error reporting is performed as described in Section 26 4 5 4 Reception Error Reporting...

Page 964: ...olled SCI Data Frame reception is shown in Figure 26 31 The RX DMA channel is used to transfer the received frame data into the memory When new data was received the module generates the receive DMA r...

Page 965: ...is generated The RWU bit is cleared and the receiver enters the Run state via the wake1 transition If the idle line wake up mode is selected and the receiver has detected an idle character The RWU bi...

Page 966: ...RSC5 and RSC5 are sampled low Noise is detected when exactly one out of the three samples is high The results of the start bit verification is summarized in Table 26 32 If the start bit verification w...

Page 967: ...sample The receiver detects the number of data bit according to the selected frame format Table 26 33 Start Bit Noise Detection RS8 RS9 RS10 Noise Detected 000 No 001 Yes 010 Yes 100 Yes 011 Yes 101 Y...

Page 968: ...ondition is fulfilled the sample counter is reset 16 RCLK cycles after the 0 of the falling edge condition was received The bit counter is not increased Figure 26 34 Data Bit Synchronization Right Shi...

Page 969: ...ity bit in the received data frame when the parity enable bit PE in the Control Register 1 eSCI_CR1 is set The parity type bit PT in the Control Register 1 eSCI_CR1 defines whether to check for odd or...

Page 970: ...me serial link To avoid the received data interrupt for frames not intended for the processor the eSCI receiver can be put into the Wakeup state If the receiver is in the Wakeup state the eSCI will st...

Page 971: ...a LIN master In conjunction with the DMA interface it is possible to transmit entire LIN frames and sequences of LIN frames as well as to receive data from LIN slaves without application intervention...

Page 972: ...d LIN frames The CRC Enhanced LIN frames shown in Figure 26 39 contain two additional CRC byte fields These fields are located between the last data field and the Checksum field The value of the CRC i...

Page 973: ...nt write accesses to the LIN Transmit Register eSCI_LTR provide data bytes to be transmitted via the LIN bus A data byte field will be transmitted as soon as data are available After the last data byt...

Page 974: ...rupt flag in the Interrupt Flag and Status Register 2 eSCI_IFSR2 will be set The application should clear the TXRDY interrupt flag before writing data into the LIN Transmit Register eSCI_LTR because t...

Page 975: ...header and the reception of the frame data automatically and utilizes the two connected DMA channels A block diagram which presents an overview of the DMA Controlled LIN RX Frame generation and recept...

Page 976: ...will also be set the LINRX register must be read before normal operations can proceed 26 4 6 5 3 Standard Bit Error Detection The standard bit error detection is performed on each byte field transmiss...

Page 977: ...hich was transmitted can be selected with the BESM bit in the Control Register 2 eSCI_CR2 If eSCI_CR2 BESM 1 the comparison will be performed with sample RS13 otherwise with RS9 see Figure 26 43 also...

Page 978: ...TFRAME_MAX when a LIN RX frame is initiated 26 4 6 5 6 Checksum Error Detection If the checksum enable bit CSE in the LIN Transmit Register eSCI_LTR was set the checksum checking is performed based o...

Page 979: ...akeup flag LWAKE in the Interrupt Flag and Status Register 2 eSCI_IFSR2 will be set Since each valid wakeup condition violates the byte field structure the frame error flag FE in the Interrupt Flag an...

Page 980: ...tart of transmission the iCMT bit was cleared Table 26 36 eSCI Interrupt Flags and Interrupt Enable Bits Interrupt Source Operational Mode Interrupt Flag Interrupt Enable Bit Transmitter SCI eSCI_IFSR...

Page 981: ...TE bit in Control Register 1 eSCI_CR1 this set the internal iPRE bit which requests the preamble transmission 4 write to SCI Data Register ESCI_DR this sets the internal iCMT bit which requests the d...

Page 982: ...Enhanced Serial Communication Interface eSCI 26 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...

Page 983: ...ut CPU or DMA interaction Each EQADC module has 24 dedicated external analog input pins and 16 pins are shared by each module The EQADC transfers commands from multiple Command FIFOs CFIFOs to the on...

Page 984: ...system RFIFOx CFIFOx ANA0 ANA23 AN24 AN39 VDDA_AN_A VDDA_DIG_A VSSA_AN_A VSSA_DIG_A VRH_A VRL_A REFBYPCA REFBYPCA1 VDDA_AN_B VDDA_DIG_B VSSA_AN_B VSSA_DIG_B VRH_B VRL_B REFBYPCB REFBYPCB1 ADC0 ADC1 RF...

Page 985: ...ecoder ADC0 ADC1 BIAS GEN REFBYPC CFIFOx NOTE x 0 1 2 3 4 5 32 bits CQueue y RQueue y System RFIFOx 16 bits CBuffer0 CBuffer1 EQADC FIFO Control MUX Control Logic Channel VDDA VSSA VRH VRL MA0 MA1 MA2...

Page 986: ...noted Table 27 1 EQADC Primary Component Descriptions Component Function FIFO Control Unit Controls the CFIFOs and the RFIFOs Prioritizes the CFIFOs to determine which CFIFOs will have their commands...

Page 987: ...ws eQADC_B to route conversion results without CPU intervention to the Decimation Filter block for signal processing Priority Based CFIFOs Supports six CFIFOs with fixed priority The lower the CFIFO n...

Page 988: ...targeted applications The repeating subqueue must be contained within the eight CFIFO0 entries To maintain compatibility CFIFO0 by default operates as it does before without streaming and with four e...

Page 989: ...indicating that it is static and that the clock input can be stopped The latter implies that as long as the platform clock is running CFIFOs can still be triggered using software triggers since no sch...

Page 990: ...nput Single ended analog input Differential analog input negative terminal Analog AN6 DAN3 1 Input Single ended analog input Differential analog input positive terminal Analog AN7 DAN3 1 Input Single...

Page 991: ...are disabled when the system clock propagates through the device 2 Can be disabled or not using configuration parameters Table 27 3 EQADC External Signals Signal Name Description AN0 DAN0 1 Single en...

Page 992: ...og input to the two on chip ADCs ANZ is a single ended analog input to one of the on chip ADCs in external multiplexed mode AN12 Single ended analog input Test 50 VREF analog output AN12 is a single e...

Page 993: ...pply pin for the ADCs and VSSA is the negative power supply pin for the ADCs Refer to electrical specifications REFBYPC Reference Bypass Capacitor The REFBYPC pin is used to connect an external bypass...

Page 994: ...DANB1 0 1 97 ANA4 and ANA5 DANA2 and DANA2 0 1 98 ANB4 and ANB5 DANB2 and DANB2 0 1 98 ANA6 and ANA7 DANA3 and DANA3 0 1 99 ANB6 and ANB7 DANB3 and DANB3 0 1 99 Temperature Sensor 0 1 128 PMC band ga...

Page 995: ...used to calibrate the EQADC Use the 25 and 75 reference points to calibrate the EQADC 3 This function is when using an external multiplexer 4 Refer to the PMC chapter Table 27 5 EQADC Memory Map Addre...

Page 996: ...ister 0 32 R W 0x0000_0000 27 6 2 6 22 0x0064 EQADC_IDCR1 EQADC Interrupt and DMA Control Register 1 32 R W 0x0000_0000 0x0068 EQADC_IDCR2 EQADC Interrupt and DMA Control Register 2 32 R W 0x0000_0000...

Page 997: ...13 37 0x0120 0x013C Reserved 0x0140 0x0 14C EQADC_CF1Rw EQADC CFIFO1 Registers w 0 3 32 R 0x0000_0000 27 6 2 13 37 0x0150 0x0 17C Reserved 0x0180 0x0 18C EQADC_CF2Rw EQADC CFIFO2 Registers w 0 3 32 R...

Page 998: ...37 0x03D0 0x 03FC Reserved 0x0400 0x0 40C EQADC_RF4Rw EQADC RFIFO4 Registers w 0 3 32 R 0x0000_0000 27 6 2 14 37 0x0410 0x0 43C Reserved 0x0440 0x0 44C EQADC_RF5Rw EQADC RFIFO5 Registers w 0 3 32 R 0x...

Page 999: ...one Table 27 6 EQADC_MCR Field Descriptions Field Description 0 23 Reserved 24 25 ICEAn Immediate Conversion Command Enable ADCn n 0 1 ICEAn enables the EQADC to abort on chip ADCn current conversion...

Page 1000: ...riod of the digital filter which is calculated according to the following equation Minimum clock counts for which an ETRIG signal needs to be stable to be passed through the filter are shown below Ref...

Page 1001: ...lso increments the corresponding EQADC_FISR CFCTRx value by one When the CFIFOx is full the EQADC ignores any write to the CF_PUSHx Reading EQADC_CFPRx always returns zero Note Only whole words must b...

Page 1002: ...ails refer to Section 27 7 4 2 CFIFO0 Streaming Mode Description 1 Enable the streaming mode of CFIFO0 0 Streaming mode of CFIFO0 is disabled 5 SSEx CFIFO Single Scan Enable Bit x The SSEx bit is used...

Page 1003: ...continued Field Description MODEx 0 3 CFIFO Operation Mode 0b0000 Disabled 0b0001 Software Trigger Single Scan 0b0010 Low Level Gated External Trigger Single Scan 0b0011 High Level Gated External Trig...

Page 1004: ...en the ATRIG0 is used to enable the ETRIG0 or to advance the command queue the normal mode of operation is external trigger single scan Other settings are not fully tested Address 0x0060 Access User r...

Page 1005: ...Ex Non Coherency Interrupt Enable x NCIEx enables the EQADC to generate an interrupt request when the corresponding EQADC_FISR NCFx is asserted 0 Disable non coherency interrupt request 1 Enable non c...

Page 1006: ...erted 0 Disable CFIFO Fill DMA or Interrupt request 1 Enable CFIFO Fill DMA or Interrupt request Note CFFEx must not be negated while a DMA transaction is in progress 7 23 CFFSx CFIFO Fill Select x CF...

Page 1007: ...n progress 14 31 RFDSx RFIFO Drain Select x RFDSx selects if a DMA or interrupt request is generated when EQADC_FISR RFDFx is asserted If RFDEx is asserted the EQADC generates an interrupt request whe...

Page 1008: ...lag x PF behavior changes according to the CFIFO trigger mode In edge trigger mode PFx is set when the EQADC completes the transfer of an entry with an asserted Pause bit from CFIFOx In level trigger...

Page 1009: ...ndependent interrupt request for a CFIFOx underflow event the EQADC also provides a combined interrupt at which the Result FIFO Overflow Interrupt the Command FIFO Underflow Interrupt and the Command...

Page 1010: ...t requests of ALL CFIFOs are ORed When RFOIEx CFUIEx and TORIEx are all asserted this combined interrupt request is asserted whenever one of the following 18 flags becomes asserted RFOFx CFUFx and TOR...

Page 1011: ...r any bytes of the corresponding EQADC_RFPR decrements RFCTRx by one Writing any value to RFCTRx itself has no effect 28 31 POPNXT PTRx RFIFOx Pop Next Pointer POPNXTPTRx indicates the index of the en...

Page 1012: ...ct Address 0x0098 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 TC_CF4 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 TC...

Page 1013: ...e 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R CFS0_TCB1 CFS1_TCB1 CFS2_TCB1 CFS3_TCB1 CFS4_TCB1 CFS5_TCB1 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R...

Page 1014: ...1110 Reserved 1111 No command was transferred to CBuffern 21 31 TC_LCFTCBn Transfer Counter for Last CFIFO to transfer commands to CBuffern TC_LCFTCBn indicates the number of commands which have been...

Page 1015: ...er EQADC_REDLCCR Table 27 15 EQADC_CFSR Field Descriptions Field Description 0 11 CFSx CFIFO Status CFSx indicates the current status of CFIFOx 00 Idle CFIFO is disabled CFIFO is in single scan edge o...

Page 1016: ...d 16 19 24 27 REDBSm Red Line Timebase Bits Selection m m 1 2 Selects 16 bits from the total of 24 bits that are received from the Red Line interface as described in below Consider TBASEm 0 23 the sel...

Page 1017: ...Rw w 0 3 Address 0x0140 0x0144 0x0148 01014C Access User read only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R CFIFO0_DATAw W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 2...

Page 1018: ...Rw w 0 3 Address 0x0200 0x0204 0x0208 01020C Access User read only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R CFIFO4_DATAw W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 2...

Page 1019: ...o its four 16 bit entries Refer to Section 27 7 5 EQADC Result FIFOs for more information on RFIFOs These registers are read only Data written to these registers is ignored Table 27 17 EQADC_CFxRw Fie...

Page 1020: ...ddress 0x0340 0x0344 0x0348 01034C Access User read only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 2...

Page 1021: ...ddress 0x03C0 0x03C4 0x03C8 0103CC Access User read only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 2...

Page 1022: ...r0 Registers ADC1_CR ADC1_GCCR ADC1_OCCR ADC1_AGR1 2 and ADC1_AOR1 2 can only be accessed by configuration commands sent to CBuffer1 Registers ADC_TSCR ADC_TBCR ADC_ACR1 8 and ADC_PUDCR0 7 can be acce...

Page 1023: ...urations Write 0x0B ADC0 ADC1 Conversion Command for Alternate Configuration 4 See Conversion Command Format for Alternate Configurations Write 0x0C ADC0 ADC1 Conversion Command for Alternate Configur...

Page 1024: ...onfiguration 7 Control Register ADC_ACR7 Write Read 0x49 Reserved 0x4A Reserved 0x4B Reserved 0x4C Alternate Configuration 8 Control Register ADC_ACR8 Write Read 0x4D 0x6F Reserved 0x70 Pull Up Down C...

Page 1025: ...ion Command Format for the Standard Configuration ADC0 Register Address 0x01 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R ADC0 _EN 0 0 0 ADC0 _EM UX 0 0 0 0 0 ADC0 _CLK _ SEL ADC0_CLK_PS W Reset 0 0 0 0 0...

Page 1026: ...tiplexer channels can be selected Note Both ADC0 and ADC1 of an eQADC module pair must be enabled before calibrating or using either ADC0 or ADC1 of the pair Failure to enable both ADC0 and ADC1 of th...

Page 1027: ...CLK_PS 0 4 Platform Clock Divide Factor 0b00000 2 0b00001 4 0b00010 6 0b00011 8 0b00100 10 0b00101 12 0b00110 14 0b00111 16 0b01000 18 0b01001 20 0b01010 22 0b01011 24 0b01100 26 0b01101 28 0b01110 30...

Page 1028: ...CBuffer1 to ADC_TSCR are not allowed ADC0 1 Register Address 0x02 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 TBC_CLK_PS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 27 34 ADC Ti...

Page 1029: ...llowed 27 6 3 4 ADC0 1 Gain Calibration Constant Registers ADC0_GCCR and ADC1_GCCR The ADC0 1 Gain Calibration Constant Register ADC0 1_GCCR contains the gain calibration constant used to fine tune th...

Page 1030: ...0 1 Gain Calibration Constant Registers ADC0 1_GCCR Table 27 26 ADC0 1_GCCR Field Descriptions Field Description 0 Reserved 1 14 GCC0 1 Gain calibration constant for ADC0 1 GCC0 1 contains the gain ca...

Page 1031: ...he alternate configurations when the conversion command with the alternate configuration format is written to an address in the range 0x08 0x0F of the on chip ADC memory map Refer to Conversion Comman...

Page 1032: ...he behavior of the FMTA bit and the FFMT bit of the conversion command for alternate configurations see Conversion Command Format for Alternate Configurations Note Decimation Filter H is only accessib...

Page 1033: ...ST field is not 0b000 the FMTA bit specifies how the 12 bit conversion data returned by the ADCs is formatted into the 16 bit data which is sent to the parallel side interface 0 Right justified unsign...

Page 1034: ...alibration constants used to fine tune ADC0 1 conversion results for alternate configurations 1 and 2 The gain calibration constants are 15 bit unsigned fixed point numbers expressed in the GCC_INT GC...

Page 1035: ...x 0 0 PULL_STRx 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 27 41 ADC Pull Up Down Control Register x ADC_PUDCRx x 0 7 Table 27 31 ADC_PUDCRx Field Descriptions Field Description 0...

Page 1036: ...ith the possibility of abortion of some current ADC conversion in progress The aborted command is stored and executed again as soon as the critical timing commands have been finished The multiple Resu...

Page 1037: ...chip ADCs are adjusted considering the selected resolution of the ADC and are formatted into result messages inside the Result Format and Calibration Sub Block This result message can be routed direct...

Page 1038: ...Command message has 32 bits and is composed of two parts a CFIFO header and an ADC Command The size of the CFIFO header is fixed to 6 bits and it works as inputs to the FIFO Control Unit It controls...

Page 1039: ...28 29 30 31 R CHANNEL_NUMBER 0 0 0 0 0 0 0 0 W ADC Command Table 27 32 Field Descriptions Field Description 0 EOQ End Of Queue Bit The EOQ bit is asserted in the last command of a CQueue to indicate t...

Page 1040: ...alibration Bit CAL indicates if the returning conversion result must be calibrated 1 Calibrate conversion result 0 Do not calibrate conversion result 8 11 MESSAGE_TAG MESSAGE_TAG Field The MESSAGE_TAG...

Page 1041: ...ch are different from the standard format will be described here Figure 27 44 Conversion Command Format for Alternate Configurations 14 TSR Time Stamp Request TSR indicates the request for a time stam...

Page 1042: ...ration mode is configured to single or continuous scan edge trigger mode 0 Do not enter WAITING FOR TRIGGER state after transfer of the current Command Message 1 Enter WAITING FOR TRIGGER state after...

Page 1043: ...ed for customer use see note 1011 1111 Reserved Note These messages are treated as null messages 12 13 LST Long Sampling Time These two bits determine the duration of the sampling time in ADC clock cy...

Page 1044: ...and Format for On Chip ADC Operation 16 23 CHANNEL_ NUMBER Channel Number Field The CHANNEL_NUMBER field selects the analog input channel The software programs this field with the channel number corre...

Page 1045: ...t be 0b0 6 BN Buffer Number Bit Refer to Section Conversion Command Format for the Standard Configuration 7 R W Read Write bit A negated R W indicates a write configuration command 0 Write1Read 8 15 A...

Page 1046: ...e CAL bit is negated this 14 bit data is obtained by executing a 2 bit left shift on the 12 bit data resultant from the resolution adjustment on the 8 or 10 or 12 bit data received from the ADC The re...

Page 1047: ...maginary ground at VREF 2 the MSB bit of the 14 bit result is inverted and is sign extended to a 16 bit format as in Figure 27 47 When FMT FFMT is negated the EQADC zero extends the 14 bit result data...

Page 1048: ...l V Corresponding 8 bit Conversion Result Returned by the ADC 3 Corresponding 10 bit Conversion Result Returned by the ADC 4 Corresponding 12 bit Conversion Result Returned by the ADC 5 16 bit Result...

Page 1049: ...MA request served by the DMAC is generated when CFFS is asserted The host CPU or the DMAC respond to these requests by writing to the EQADC_CFPR to fill the CFIFO NOTE The DMAC should be configured to...

Page 1050: ...FO Using TNXTPTR and CFCTR the absolute addresses for the entries indicated by the Transfer Next Data Pointer and by the Push Next Data Pointer can be calculated using the following formulas Transfer...

Page 1051: ...led behavior of the Push Next Data Pointer and Transfer Next Data Pointer is described in the example shown in Figure 27 50 where a CFIFO with 16 entries is shown for clarity of explanation the actual...

Page 1052: ...REP bit Push Transfer CFIFOx First In After reset or invalidation Next Data Pointer Next Data Pointer Last In Valid Entry Empty Entry Push Transfer CFIFOx Some entries pushed but none Executed Next D...

Page 1053: ...bit is completed then the queue stops and enters the Pause state waiting for a trigger This is the same as normal behavior The Pause state is exited in one of two ways Repeat Trigger or Repeat Trigge...

Page 1054: ...IFO0 is not starting a new loop In this case outside a loop if a PAUSE bit is decoded this means to disable the Repeat trigger detector This can be useful if the Repeat trigger is not required for som...

Page 1055: ...where a CFIFO with 16 entries is shown for clarity of explanation the actual hardware implementation has only four eight entries In this example CFIFO0 with 16 entries is shown in sequence after push...

Page 1056: ...t Data Pointer Transitory state Repeat trigger with no Entries pushed but not Repeat Pointer Repeat Pause up to pause bit waiting for trigger Repeat Pause Repeat Pointer Transfer CFIFO0 Next Data Poin...

Page 1057: ...f Queue bit EOQ continues to operate as in normal mode unless the Repeat mode is enabled In this case the Pause bit takes precedence and a Repeat trigger causes the jump back described A Repeat trigge...

Page 1058: ...gic of the EQADC depicted in Figure 27 54 is composed of two independent sub blocks one prioritizing CFIFOs with commands bound for CBuffer0 and another prioritizing CFIFOs with commands for CBuffer1...

Page 1059: ...r and the sampling of the command from Cqueue0 can be unacceptable EQADC can be configured to permit immediate conversion commands from CFIFO0 with abort function When CFIFO0 is triggered and abort is...

Page 1060: ...ilter logic level one in rising edge external trigger mode The EQADC can detect rising edge falling edge or level gated external triggers The digital filter will always be active independently of the...

Page 1061: ...trigger to transferring a command is a function of clock frequency trigger synchronization trigger filtering or not programmable trigger events command transfer CFIFO prioritization CBuffer availabili...

Page 1062: ...l trigger mode the respective triggers are only detected when the SSS bit is asserted When the SSS bit is negated all trigger events for that CFIFO are ignored Writing a 1 to the SSE bit can be done d...

Page 1063: ...EQADC clears the SSS bit and stops transferring commands from a TRIGGERED CFIFO when an asserted EOQ bit is encountered or when CFIFO status changes from TRIGGERED due to the detection of a closed gat...

Page 1064: ...ing commands from a TRIGGERED CFIFO when CFIFO status changes from TRIGGERED due to the detection of a closed gate If a closed gate is detected while no command transfers are taking place and the CFIF...

Page 1065: ...e CFIFO when CFIFO status changes from TRIGGERED due to the detection of a closed gate 5 NOTES 1 Refer to Section 27 7 4 7 2 CQueue Completion Status for more information on EOQ 2 Refer to Section 27...

Page 1066: ...TING FOR TRIGGER 0b10 CFIFO Mode is programmed to continuous scan edge or level trigger mode OR CFIFO Mode is programmed to single scan edge or level trigger mode and SSS is asserted OR CFIFO Mode is...

Page 1067: ...not modified to disabled OR CFIFO in single scan level trigger mode and the gate closes while no commands are being transferred from the CFIFO and CFIFO Mode is not modified to disabled OR CFIFO in si...

Page 1068: ...set when CFIFO status changes from TRIGGERED due to detection of a closed gate The pause flag interrupt routine can be used to verify if the a complete scan of the CQueue was performed If a closed ga...

Page 1069: ...herent if while it is transferring commands to a CBuffer the buffer is only fed with commands from that sequence without ever becoming empty A command sequence starts when a CFIFO in TRIGGERED state t...

Page 1070: ...5_CB1_CM3 CF5_CB0_CM4 CF5_CB2_CM5 CF5_CB1_CM6 EOQ 1 command sequences Example 3 Example 1 Example 2 CQueue with a two command sequences Assuming that these commands are transferred by a CFIFO configur...

Page 1071: ...ter the first command transfer from the preempting CFIFO that is the higher priority CFIFO to the CBuffer in use is completed See Figure 27 58 Once command transfers restart continue the non coherency...

Page 1072: ...CF5_CB1_CM2 2 CF5_CB1_CM3 3 CF0_CB1_CM0 0 CF0_CB1_CM1 1 CF0_CB1_CM2 2 CF0_CB1_CM3 3 TNXTPTR CF5_CB1_CM0 0 CF5_CB1_CM1 1 CBuffer1 CFIFO5 CFIFO0 TNXTPTR Sent 0 Sent 1 CF5_CB1_CM2 2 CF5_CB1_CM3 3 Sent 0...

Page 1073: ...se requests by reading Section 27 6 2 4 EQADC Result FIFO Pop Registers EQADC_RFPR to retrieve data from the RFIFO NOTE The DMAC should be configured to read a single result 16 bit data from the RFIFO...

Page 1074: ...RFIFO four in this implementation When a new message arrives and RFIFOx is not full the EQADC copies its contents into the entry pointed by the Receive Next Data Pointer The RFIFO counter RFCTRx in Se...

Page 1075: ...hardware implementation has only four entries In this example RFIFOx with 16 entries is shown in sequence after popping or receiving entries Data Entry 2 Data Entry 1 POP Next Data Pointer Receive Ne...

Page 1076: ...et or invalidation Next Data Pointer Next Data Pointer Last In Valid Entry Empty Entry Receive Pop RFIFOx Some entries received but none popped Next Data Pointer Next Data Pointer Pop RFIFOx No entrie...

Page 1077: ...n consecutive clock cycles in order to guarantee they are always stored in consecutive RFIFO entries 27 7 6 On Chip ADC Configuration and Control 27 7 6 1 Enabling and Disabling the On chip ADCs The o...

Page 1078: ...is set the ADC clock frequency is the same as the platform clock but it has the inverted phase When it is clear the ADC0 1_CLK_PS field selects the clock divide factor by which the platform clock will...

Page 1079: ...would result in a ADC clock frequency higher than the maximum one supported by the ADC In this example the maximum ADC clock frequency is 15 MHz 12 bits resolution conversions with unitary input gain...

Page 1080: ...led The time base counter can be reset by writing 0x0000 to the Section 27 6 3 3 ADC Time Base Counter Registers ADC_TBCR with a write configuration command 27 7 6 4 ADC Pre gain Feature Each ADC can...

Page 1081: ...ain calibration constant RAW_RES is the raw uncalibrated result with resolution adjustment corresponding to an specific input voltage Vi OCC is the offset calibration constant The addition of two redu...

Page 1082: ...its fractional part GCC_FRAC GCC 2 15 contains 14 bits see Figure 27 64 The gain constant equivalent decimal value ranges from 0 to 1 999938 as shown in Table 27 41 Two is always added to the MAC outp...

Page 1083: ...ister a conversion result or a time stamp The formatting and calibration of conversion results also take place inside this sub block The Time Stamp Logic latches the value of the time base counter whe...

Page 1084: ...the internal capacitance of the multiplexers will be settled by that time allowing for more accurate sampling This is specially important for applications that require high conversion speeds that is...

Page 1085: ...0 TSR0 MESSAGE_TAG1 FMT1 CAL1 EMUX1 TBC_CLK_PS 32 bits MA0 MA1 MA2 ENTRY1 ENTRY0 Configuration ENTRY1 ENTRY0 TSR1 ADDR or and DATA ADDR or and DATA Register Data 0 1 CHANNEL_NUMBER0 Time Stamp1 Regist...

Page 1086: ...a secondary multiplexer that are used to monitor signals internal to the chip These analog input pins are also selected by the CHANNEL_NUMBER field Channel Change and Sample Start a Command Execution...

Page 1087: ...t signal Conversion type b d 0000_0000 0 0 1 X AN0 accessible when DAN0 and DAN0 are not being accessed Single ended 0000_0001 1 0 1 X AN1 accessible when DAN0 and DAN0 are not being accessed Single e...

Page 1088: ...nded 0101_0xxx 80 to 87 0 1 1 ANY the MA2 MA0 pins act as the selector inputs for an external 8 to 1 mux see also AN10 Single ended 0101_1xxx 88 to 95 0 1 1 ANZ the MA2 MA0 pins act as the selector in...

Page 1089: ...nded 1010_1000 to 1100_0001 168 to 193 Reserved 1100_0010 194 X 0 INA_ADC1_3 see Table 27 4 Single ended 1100_0011 195 X 0 INA_ADC1_4 see Table 27 4 Single ended 1100_0100 196 X 0 INA_ADC1_5 see Table...

Page 1090: ...lexed address signals are connected to all eight external multiplexer chips The analog output of the eight multiplex chips are each connected to eight separate EQADC inputs ANR ANS ANT ANU ANW ANX ANY...

Page 1091: ...AN84 AN85 AN86 AN87 MUX AN88 AN89 AN90 AN91 AN92 AN93 AN94 AN95 ANW ANX ANY ANZ 4 AN0 AN7 32 40 MUX 40 1 MUX 40 1 ADC0 ADC1 MUX CONTROL Channel Number0 1 EQADC AN12 AN15 NOTE Limited availability of p...

Page 1092: ...Registers EQADC_IDCR Interrupt Condition Clearing Mechanism Non Coherency Interrupt NCIEx 1 NCFx 1 Clear NCFx bit by writing a 1 to the bit Result FIFO Overflow Interrupt2 2 Apart from generating an...

Page 1093: ...Freescale Semiconductor 27 111 PXR40 Microcontroller Reference Manual Rev 1 NOTES 1 For details refer to Section 27 6 2 7 EQADC FIFO and Interrupt Status Registers EQADC_FISR and Section 27 6 2 6 EQA...

Page 1094: ...OQIEx EOQFx CFUIEx CFUFx RFOIEx RFOFx Non Coherency Interrupt Request Pause Interrupt Request End of Queue Interrupt Request Trigger Overrun Interrupt Request CFIFO Underflow Interrupt Request RFIFO O...

Page 1095: ...SD stage and then from the RSD stage output back to its input to be passed again To complete a 12 bit conversion the signal must pass through the RSD stage 12 times For 10 bit and 8 bit resolution the...

Page 1096: ...on the two comparator inputs As the Logic Control sets the summing operation it also sends a digital value to the RSD adder Each time an analog signal passes through the RSD single stage a digital va...

Page 1097: ...nput phase and after each of the 12 passes through the RSD stage Thus 13 total a and b values are collected Upon collecting all these values they will be added according to the RSD algorithm to create...

Page 1098: ...mes before the normal conversion processing 27 8 Initialization Application Information 27 8 1 Multiple Queues Control Setup Example This section provides an example of how to configure multiple CQueu...

Page 1099: ...h as timers In order to avoid unexpected triggering of CFIFOs in hardware trigger modes the source driving the ETRIG port must be selected and set to a known logic level before putting the CFIFOs into...

Page 1100: ...iguration command in CFIFO0 that enables ADC0 ADC0_EN 1 and that sets the ADC0_CLK_PS to an appropriate value For example 0x80800801 2 Push an ADC1_CR write configuration command in CFIFO1 that enable...

Page 1101: ...own in Table 27 47 c Results will be returned to RFIFO3 as specified in the MESSAGE_TAG field of commands 2 Reserve memory space for storing results Table 27 47 Example of CQueue Commands1 NOTES 1 Fie...

Page 1102: ...Set RFDE3 and CFFE1 to enable the EQADC to generate DMA requests Command transfers from the RAM to the CFIFO1 will start immediately e Set RFOIE3 to indicate if RFIFO3 overflows f Set CFUIE1 to indic...

Page 1103: ...rred cyclic queue or the first command of any other CQueue This is desirable for CFIFOs in continuous scan mode and at some cases for CFIFOs in single scan mode Figure 27 74 CQueue CFIFO Interface 27...

Page 1104: ...rol Registers EQADC_IDCR a Clear CFIFO Fill Enable5 CFFE5 0 in EQADC_IDCR2 b Clear CFIFO Underflow Interrupt Enable5 CFUIE5 0 in EQADC_IDCR2 c Clear RFDS5 to configure the EQADC to generate interrupt...

Page 1105: ...ter EQADC_CFSR c Read and save TC_CFx in Section 27 6 2 8 EQADC CFIFO Transfer Counter Registers EQADC_CFTCR for later resuming the scan of the queue The TC_CFx provides the point of resumption d Sinc...

Page 1106: ...ome only configure them and do not request returning data When a CQueue contains both write and read commands like CQueue0 the CQueue and RQueue entries will not be aligned as shown in Figure 27 76 th...

Page 1107: ...to RQueue1 CQueue1 Read Command 1 0x0004 Result to RQueue1 CQueue1 Conversion Command 2 0x0008 Result to RQueue1 CQueue1 Conversion Command m 0x001C Command Queue 1 CQueue1 Result CQueue1 Read Command...

Page 1108: ...bit negated The transfer equations for when sampling these reference voltages are CAL_RES75 VREF GCC RAW_RES75 VREF OCC 2 CAL_RES25 VREF GCC RAW_RES25 VREF OCC 2 Thus GCC CAL_RES75 VREF CAL_RES25 VREF...

Page 1109: ...2 Example The raw results obtained when sampling reference voltages 25 VREF and 75 VREF were respectively 3798 and 11592 The results that should have been obtained from the conversion of these referen...

Page 1110: ...es a comparison between the EQADC and QADC in terms of their functionality This section targets the users familiar with terminology in QADC Figure 27 78 is an overview of a QADC Figure 27 79 is an ove...

Page 1111: ...ed with the QADC the EQADC system requires extra hardware 1 A DMA or an MCU is required to move data between the EQADC s FIFOs and Queues in the system memory External Triggers Result Queues Command Q...

Page 1112: ...CWPQx Counter Value of Commands Transferred from Command FIFOx TC_CFx In the QADC CWPQx allows the last executed command on queue x to be determined In the EQADC the TC_CFx value allows the last trans...

Page 1113: ...ueues and Buffers Not Required Program the DMAC or the CPU to handle the data transfer Queue Execution Require Software or External Trigger events to start queue execution Require Software or External...

Page 1114: ...Enhanced Queued Analog to Digital Converter EQADC 27 132 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...

Page 1115: ...rdware link to Decimation Filters A through L This allows CPU independent transfer of eQADC_A and eQADC_B analog to digital conversion result data to the Decimation Filter input data registers and fil...

Page 1116: ...put buffer overruns occur An interrupt can also be generated when an integrator result is ready to be read Figure 28 1 shows a system level block diagram of a single Decimation Filter All Decimation F...

Page 1117: ...lock Diagram AN n RFIFO ADC eQADC_B 51 bit MAC 4th order Decimator Rate Interrupts Coeff Decimation Filter Block CPU Interrupt Controller Peripheral Bridge B eTPUA eDMA_B eDMA_A 1 to 16 Peripheral Bri...

Page 1118: ...status configuration registers and data input output Filter initialization flush and stabilization prefill commands Timestamp support Programmable integer decimation rates of 1 to 16 32 bit fixed poin...

Page 1119: ...28 2 2 Decimation Filter Register Descriptions The base address of each Decimation Filter block is given in Table 28 2 28 2 1 Decimation Filter Memory Map The addresses of the Decimation Filter regist...

Page 1120: ...28 2 2 7 28 20 DECFILT_x_ BASE 0x034 DECFILTER_COEF5 Filter Coefficient 5 32 R W 0x0000_0000 28 2 2 7 28 20 DECFILT_x_ BASE 0x038 DECFILTER_COEF6 Filter Coefficient 6 32 R W 0x0000_0000 28 2 2 7 28 2...

Page 1121: ...0x0000_0000 28 2 2 8 28 21 DECFILT_x_ BASE 0x094 DECFILTER_TAP7 Filter TAP 7 Register 32 R 0x0000_0000 28 2 2 8 28 21 DECFILT_x_ BASE 0x098 0x0CF Reserved DECFILT_x_ BASE 0x0D0 DECFILTER_EDID Enhance...

Page 1122: ...3 8 Freeze Mode for more details 0 Freeze mode disabled 1 Freeze mode enabled 2 Reserved 3 FRZ Freeze Mode Controls the freeze mode of the Decimation Filter For this bit to take effect the FREN freez...

Page 1123: ...tion of the filter output See Section 28 3 11 Saturation for more details 0 Disables Saturation 1 Enable Saturation 18 19 IO_SEL Input Data Source and Output Result Destination Selection Selects the s...

Page 1124: ...receive new data eQADC input is selected with Enhanced debug IO_SEL 1 0 EDME 1 DSEL 0 and the input buffer has data to be read by the CPU 0 Input Buffer Interrupt Request Disabled 1 Input Buffer Inte...

Page 1125: ...The DEC_COUNTER 3 0 field indicates the current value of the DEC_COUNTER Decimation Counter which counts the number of input data samples received by the Decimation Filter When the value of this count...

Page 1126: ...te OBS This flag is not used for read write requests It is used only to announce the input data event For read write request flag refer to IBIF 23 ODF Output Data Flag The ODF bit flag indicates when...

Page 1127: ...rrun The OVR bit indicates that a decimated sample was overwritten by a new sample in the Interface Output Buffer Register This flag generates an Interrupt Request if enabled by the ERREN bit in the C...

Page 1128: ...rted with signed integration therefore one must not configure SSIG 1 and SSAT 0 3 SCSAT Integrator Counter Saturated operation selection The SCSAT bit defines how the integrator sample counter behaves...

Page 1129: ...XCR bit SDMAE and DECFILT_x_MCR bit SDIE When continuous output is on an integrator output request is issued whenever a new filter output is accumulated For more details see Section 28 3 13 2 Integrat...

Page 1130: ...SDFC SSEC SCEC SSOVF C SCOVF C SVRC Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 SDF 0 0 SSE SCE 0 SSOVF SCOVF SVR W Reset 0 0 0 0 0 0 0 0 0 0...

Page 1131: ...ed 23 SDF Integrator Data Flag The SDF bit flag indicates when a new integrator result is available at the DECFILT_x_FINTVAL register This flag generates an Interrupt Request if enabled by the SDIE bi...

Page 1132: ...s cleared by the SCOVFC bit or by a soft reset 0 No overflow in the integrator sample counter 1 Integrator sample counter overflown Note The SCOVF bit samples the integrator accumulator overflow condi...

Page 1133: ...7 INTAG Decimation filter input tag bits The INTAG 3 0 bit field is defined as a selector signal and it is used to identify different destinations for the INBUF 15 0 data When the input data source i...

Page 1134: ...as a selector signal and it is used to identify different destinations for the OUTBUF 15 0 data When the output result destination is an eQADC OUTTAG holds the same value as the DECFILT_x_IB INTAG wh...

Page 1135: ...0x078 0x094 Access User read only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 8 TAPn 23 TAPn 23 16 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R TAPn 15 0 W Res...

Page 1136: ...ASE 0x0D0 Access User read only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R SAMP_D...

Page 1137: ...ned number otherwise Note If SSAT 0 DECFILT_x_FINTVAL holds the integration sum modulo 217 considering the 15 bit fractional part Note If SSAT 1 the integration sum is saturated so that if the accumul...

Page 1138: ...d holds an unsigned number representing the sum of filtered output values continuously updated as the integration proceeds The control of the integration sum is determined by the register DECFILT_x_MX...

Page 1139: ...by software write to the IDFC bit See Section 28 3 12 Interrupts and DMA Overview for more information on interrupt and DMA requests 28 3 1 1 Input Buffer Overrun An input overrun occurs when the inp...

Page 1140: ...ed when the DECFILT_x_MCR DSEL 1 and the output buffer is updated If DMA is not enabled an interrupt is generated by setting the DECFILT_x_MCR OBIE 1 If both an interrupt and DMA request are enabled t...

Page 1141: ...tput should be generated while the control field indicates prefill Therefore the prefill function is used in the beginning of the filter operation to initialize and stabilize the Decimation Filter wit...

Page 1142: ...if the corresponding received conversion data has generated a filter output that is selected by the decimation counter to be sent to the output buffer Other received timestamps that come with data not...

Page 1143: ...DECFILT_x_MCR is also not affected by a soft reset except for the self negation of the SRES bit When in debug or freeze mode the soft reset is executed but the filter remains in debug or freeze mode...

Page 1144: ...even number which makes the decision on rounding up or down based on the value of the lower portion of data to be rounded LS_WORD The rounding up down condition is equal to the traditional rounding e...

Page 1145: ...can receive data when a word of output data is available when an error has occurred The input data flag DECFILT_x_MSR IDF is set when a new input data is received from the CPU or an eQADC Note that t...

Page 1146: ...re detail in Section 28 3 12 1 3 Input Buffer DMA Request Section 28 3 12 2 2 Output Buffer DMA Request and Section 28 3 12 3 Integrator Interrupt and DMA Requests 28 3 12 1 Input Buffer Interrupt and...

Page 1147: ...rocessed As this filter register is overwritten by the next word of sample data a DMA read overrun event can occur the DECFILT_x_MSR DIVR bit is asserted if the DMA request is not cleared before or at...

Page 1148: ...ration Figure 28 17 shows the high level data flows and controls for the integrator The RFIFO and Output Buffer data paths are shown in this figure to highlight that they are independent of the integr...

Page 1149: ...e value of 0xFFFFFFFF for absolute value accumulation SSIG 0 or 0x7FFFFFFF positive and 0x80000000 negative for signed accumulation SSIG 1 non saturated accumulation SSAT 0 so that an overflow results...

Page 1150: ...ew sample is accumulated DECFILTER_CINTCNT is updated only when DECFILTER_CINTVAL is read so that coherency between the value and count values is guaranteed Therefore the read access order of that pai...

Page 1151: ...re accumulated when the integrator is enabled and not halted The integrator halt and enable states can be controlled in the following ways by hardware through eTPU2 channels the enabling and the selec...

Page 1152: ...ed SCE asserts together with SCOVF In Non saturated operation DECFILTER_MXCR SCSAT 0 a counter exception occurs SCE 1 when an overflow is flagged and the DECFILTER_MXSR bit SCOVF is already set to 1 I...

Page 1153: ...must be sequential that is Filter A feeds Filter B which feeds Filter C etc As a consequence of the conditions above there must be one and only one head block and one and only one tail block in a cas...

Page 1154: ...rsion data and the eQADC RFIFOs as destination for the outputs of the filter s Figure 28 18 Cascaded Filters Figure 28 19 Multiple Cascaded Filters eQADC RFIFOs DECFILT_B middle DECFILT_C tail CPU Con...

Page 1155: ...block in the sequence Each block in a new cascade combo must be configured with its input disabled When the mode configuration is done the combo blocks must have their inputs enabled in order from th...

Page 1156: ...se cases and configurations of the decimation filter block 28 4 1 eQADC Configuration for Decimation Filter Operation 28 4 1 1 eQADC Configuration Decimation Filter Input In normal mode of operation o...

Page 1157: ...ations are stored in the ADC by executing write commands to the On Chip ADC Alternate Configuration Registers The write command is specified in the Write Configuration Command Format for On Chip ADC O...

Page 1158: ...ee Conversion Command Format for Alternate Configurations FMTA Conversion Data Format for Alternate Configuration If the DEST field is not 0b000 the FMTA bit specifies how the 12 bit conversion data r...

Page 1159: ...erred into the filter and subsequent filtered data extracted using CPU interaction For all uses cases the Decimation Filter is configured as an IIR filter with example filter characteristics An explan...

Page 1160: ...the feed forward filter coefficients M is the number of feed back filter coefficients and Aj are the feedback filter coefficients In order to optimize the hardware implementation the coefficients mus...

Page 1161: ...x_COEF5 to DECFILT_x_COEF8 The delay taps labelled Tap0 to Tap7 correspond to the memory mapped registers DECFILT_x_TAP0 to DECFILT_x_TAP7 Figure 28 23 Fourth Order IIR Filter Implementation Block Dia...

Page 1162: ...r was previously configured by writing DECFILT_x_MCR SRES 1 Table 28 19 Computed Coefficient Values Coefficient Decimal Value Coefficient Decimal Value B0 0 0221455 A0 1 0 B1 0 00445582948893748 A1 2...

Page 1163: ...conversion and filtering The input to Filter A is from an ADC conversion result Filter A is configured as a 4rd order low pass IIR The output from the filter is routed to RFIFO5 and transferred to me...

Page 1164: ...REG_ADDRESS 0x30 set the bit field ADC_REGISTER LOW BYTE 0x00 set the bit field ADC_REGISTER HIGH BYTE 0x06 28 5 2 1 4 eQADC Command To cause the ADC conversion to be transferred to the Decimation fil...

Page 1165: ...iguration or commands are needed to support the Decimation Filter operation Decimation is not enabled Saturation is enabled 28 5 2 2 1 DECFILT_C_MCR Module Configuration Register settings Enable inter...

Page 1166: ...Decimation Filter and enable interrupts by lowering the processor priority When the interrupt occurs if DECFILT_C_MSR OBIF 1 then this indicates filter output data is available In this case read the D...

Page 1167: ...Decimation Filter Freescale Semiconductor 28 53 PXR40 Microcontroller Reference Manual Rev 1...

Page 1168: ...Decimation Filter 28 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...

Page 1169: ...ms at high resolution timing capabilities From a system perspective high resolution timing is limited by Host CPU overhead required for servicing timing tasks such as period measurement pulse measurem...

Page 1170: ...configuration Figure 29 1 eTPU A B Module Block Diagram eTPU Engine is responsible for processing input pin transitions and output pin waveform generation based on the Time Bases Each eTPU Engine has...

Page 1171: ...he Host CPU Each Channel is associated with a Function which defines its behavior the Function is a software entity consisting within the eTPU of a set of microengine routines that attend to Service R...

Page 1172: ...eTPU is sometimes used in place of eTPU Engine 29 1 1 1 1 Time Bases Two 24 bit counters TCR1 and TCR2 provide reference time bases for all match and input capture events Prescalers for both time base...

Page 1173: ...s Channel modes available can do ordered or unordered match Some modes are also provided that can block one match by the occurrence of the other Service request can be generated on one or both of the...

Page 1174: ...he Host as byte 16 bit or 32 bit wide eTPU can access it as full 32 bits lower 24 bits or upper byte 8 bit The host can also access the SDM space mirrored in other area with Parameter Signal Extension...

Page 1175: ...gradation by interleaving their accesses the Shared Code Memory has one clock access time Instruction width is 32 bits The microengine instruction set provides basic arithmetic and logic operations fl...

Page 1176: ...f second time base prescaler first time base can also be clocked by external signal with programmable prescaler division of 1 to 256 second time base clocked by external signal with programmable presc...

Page 1177: ...another begins to service a request from other Channel Channel specific registers flags and parameter base address are automatically loaded for the next serviced channel individual channel priority se...

Page 1178: ...ther unrelated instructions Multiplication supports any data width of both operands 8 16 or 24 bits signed or unsigned A 24x24 Multiply MAC result is available after four other unrelated instructions...

Page 1179: ...nd 2 besides channel 0 can now be selected to control the EAC Section 29 2 6 1 ETPUTBCR eTPU Time Base Configuration Register Timebase prescalers are now reset when the GTBE input is negated guarantee...

Page 1180: ...an be cleared and enabled disabled An Engine only enters Module Disable Mode when any currently running thread is finished Refer to the eTPU Reference Manual for details Stop Mode Stop Mode is entered...

Page 1181: ...ignal input 29 2 2 Detailed Signal Descriptions 29 2 2 1 eTPU Channel Output Signals 0 31 Each channel output signal is associated with a channel The microcode may affect the logic level of an output...

Page 1182: ...ngle Mode Like the channel input signals the TCRCLK signal has an associated synchronizer followed by a digital filter This digital filter can work in two sub modes whose purpose is to filter out nois...

Page 1183: ...ative to the eTPU Base addresses given in Table 29 3 SCM unused area is decoded and returns a fixed opcode defined in the register ETPUSCMOFFDATAR 20 B 0 to 7 21 8 to 15 22 16 to 23 23 24 to 31 Table...

Page 1184: ...r 32 R W 0x0000_0000 29 2 5 2 29 22 0x08 Reserved 0x0C ETPUMISCCMPR eTPU MISC Compare Register 32 R W 0x0000_0000 29 2 5 3 29 23 0x10 ETPUSCMOFFDATAR eTPU SCM Off range Data Register1 32 R W 0xf3775ff...

Page 1185: ...t Overflow Status Register 32 R W 0x0000_0000 29 2 9 3 29 37 0x224 ETPUCIOSR_B eTPU B Channel Interrupt Overflow Status Register 32 R W 0x0000_0000 29 2 9 3 29 37 0x228 0x22C Reserved 0x230 ETPUCDTROS...

Page 1186: ...F0 ETPUC31CR_A eTPU A Channel 31 Configuration Register 32 R W 0x0000_0000 29 2 10 1 29 43 0x5F4 ETPUC31SCR_A eTPU A Channel 31 Status and Control Register 32 R W 0x0000_0000 29 2 10 2 29 45 0x5F8 ETP...

Page 1187: ...0x8000 0x97FF SPRAM Shared Parameter RAM 0xC000 0xFFFF SPRAM Shared Parameter RAM PSE mirror 2 0x10000 0x15FFF3 SCM Shared Code Memory4 1 This register is not implemented in some MCUs see Section 29 2...

Page 1188: ...t an illegal instruction was decoded in Engine 1 2 This bit is cleared by host writing 1 to GEC See the eTPU Reference Manual for more details 1 Illegal Instruction detected by eTPU A B 0 Illegal Inst...

Page 1189: ...CMMISF transitions from 0 to 1 disabling the MISC operation VIS SCM Visibility Bit VIS bit turns SCM visible to the IP Bus and resets MISC state but SCMMISEN keeps its value 1 SCM is visible to the sl...

Page 1190: ...ermine the absolute word offset from the SDM base of the parameters to be transferred Parameter 0 word address CTBASE PARM0 SDM base word address Parameter 1 word address CTBASE PARM1 SDM base word ad...

Page 1191: ...be transferred coherently The parameter pointed by CTBASE PARM0 is the first transferred 29 2 5 3 ETPUMISCCMPR eTPU MISC Compare Register ETPUMISCCMPR holds the 32 bit signature expected from the who...

Page 1192: ...has its own ETPUECR register ETPUECR holds configuration and status fields that are programmed independently in each Engine Figure 29 7 ETPUECR Register FEND Force End Base 0x010 0 1 2 3 4 5 6 7 8 9...

Page 1193: ...gine runs Stop completes on the next eTPU clock after the stop condition is valid The MDIS bit is write protected when VIS 1 NOTE Once MDIS is switched from 1 to 0 or vice versa it must not be written...

Page 1194: ...signals and TCRCLK input as shown in Table 29 6 Filtering can be controlled independently by Engine but all input digital filters in the same Engine have same clock prescaling For more details see Se...

Page 1195: ...TCR2 There is one of each of these registers for each eTPU Engine NOTE Writes to this register issue bus error and are ineffective when MDIS 1 Reads are always allowed Table 29 7 Channel Digital Filte...

Page 1196: ...ESET 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R TCR1CTL TCR1 CS 0 0 0 0 0 TCR1P W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved Table 29 8 TCR2...

Page 1197: ...s Client see Section 29 3 5 3 STAC Interface the EAC operation is not allowed and if AM is set the Angle Logic does not work properly NOTE Changing AM may cause spurious transition detections on the c...

Page 1198: ...S 1 also makes the channel work on T2 T4 timing mode see eTPU Reference Manual for details NOTE The clock source of the EAC angle tick generator will still be an even division of eTPU clock if TCR1CS...

Page 1199: ...time base for host read access see Section 29 3 5 Time Bases This register is read only The value of the TCR2 time base shown can be driven by the TCR2 counter the Angle Mode logic or imported from S...

Page 1200: ...the functionality of TCR2 For Server mode external plugging determines the unique server address assigned to each TCR For a Client mode the SRV1 and SRV2 fields determine the Server address to which t...

Page 1201: ...the engine Figure 29 12 ETPUWDTR Register WDM Watchdog Mode WDM selects the Watchdog operation mode as shown in Table 29 12 For more information on the Watchdog operation see Section 29 3 1 Watchdog...

Page 1202: ...T 31 0 Idle Count This is a free running count of the number of idle microcycles in the microengine For more information on idle counter operation see Section 29 3 7 1 Idle Counter ICLR Idle Clear Thi...

Page 1203: ...trol registers see Section 29 2 10 Channel Configuration and Control Registers and Host must write 1 to clear a status bit Figure 29 15 ETPUCISR Register CISx Channel x Interrupt Status eTPU A Base 0x...

Page 1204: ...are writing 1 to DTRCx or by the assertion of corresponding DMA completion acknowledge line 1 indicates that channel x has a pending data transfer request 0 indicates that channel x has no pending dat...

Page 1205: ...x Channel x Interrupt Overflow Clear 1 clear status bit 0 keep status bit unaltered For details about interrupt overflow see Section 29 3 2 2 2 Interrupt and Data Transfer Request Overflow eTPU A Base...

Page 1206: ...Clear 1 clear status bit 0 keep status bit unaltered For details about data transfer request overflow see Section 29 3 2 2 2 Interrupt and Data Transfer Request Overflow eTPU A Base 0x230 eTPU B Base...

Page 1207: ...he Channel Configuration registers see Section 29 2 10 2 ETPUCxSCR eTPU Channel x Status Control Register Figure 29 20 ETPUCDTRER Register eTPU A Base 0x240 eTPU B Base 0x244 0 1 2 3 4 5 6 7 8 9 10 11...

Page 1208: ...ce Request pending for channel x Pending SR status is a logic OR of all service requests pending if only HSR is active SRx clears only at the end of the thread SRx clear due to the other request sourc...

Page 1209: ...decoding of the CHAN register since the later can be changed by the service thread microcode Figure 29 22 ETPUCSSR Register SSx Service Status x Indicates that channel x is currently being serviced It...

Page 1210: ...g the following equation Channel_Register_Base ETPU_Engine_Channel_Base channel_number 0x10 where ETPU_Engine_Channel_Base ETPU_Base 0x400 for Engine 1 ETPU_Engine_Channel_Base ETPU_Base 0x800 for Eng...

Page 1211: ...tails DTRE Channel Data Transfer Request Enable this bit is mirrored from ETPUCDTRER see Section 29 2 9 6 ETPUCDTRER eTPU Channel Data Transfer Request Enable Register 1 Enable data transfer request f...

Page 1212: ...ence Manual for details The Function assigned to the channel has to be compatible with the channel condition encoding scheme selected by field ETCS ODIS Output Disable This bit enables the channel to...

Page 1213: ...2 9 1 ETPUCISR eTPU Channel Interrupt Status Register See also the eTPU Reference Manual for details CIOS Channel Interrupt Overflow Status 1 interrupt overflow asserted for this channel 0 interrupt...

Page 1214: ...2 Interrupt and Data Transfer Request Overflow IPS Channel Input Pin State This bit shows the current value of the filtered channel input signal state OPS Channel Output Pin State This bit shows the...

Page 1215: ...2 5 Host Service Requests 29 3 Functional Description 29 3 1 Watchdog Each engine has a watchdog mechanism to prevent a thread or a sequence of threads from running too long impacting the latency of...

Page 1216: ...must not be enabled when the microengine enters halt mode The counter does not run when the engine is stopped and resets when the watchdog is disabled 29 3 2 Host Interface 29 3 2 1 System Configurat...

Page 1217: ...e is flagged by the bits ILF1 and ILF2 in register ETPUMCR An SCM signature mismatch detected by the Multiple Input Signature Calculator MISC See Section 29 3 6 1 SCM Test Multiple Input Signature Cal...

Page 1218: ...ess all 32 bits or only the lower 24 bits with an automatic sign extension see Section 29 3 2 3 4 Parameter Sign Extension Area 29 3 2 3 2 Parameter Addresses and Endianness To access parameter number...

Page 1219: ...meters before calculations and from read modify write accesses to modify 24 bit parameters at the SDM 29 3 2 4 SDM Organization The SDM internal partition for channel allocation is dynamic and program...

Page 1220: ...x16E ETPU2 Channel 3 Parameters ETPU2 Channel 0 Parameters ETPU1 Channel 0 Parameters ETPU1 Channel 1 Parameters ETPU2 Channel 30 Parameters ETPU2 Channel 2 Parameters ETPU1 Channel 2 Parameters ETPU1...

Page 1221: ...e is 000 no service thread is executed for the HSR The scheduling of HSRs is completely asynchronous with Host accesses and there is no race free manner to change an HSR value before service thread ex...

Page 1222: ...ost can program the register at initialization with an opcode value with operations that try to protect or recover the system from runaway code for instance terminate the thread clear channel flags di...

Page 1223: ...n length At any time an arbitrary number of channels can require service To request service channel logic eTPU microcode or Host application notifies the Scheduler by issuing a Service Request 29 3 3...

Page 1224: ...ng service regardless of their priority level The primary scheme prioritizes requesting channels that have different priority levels the secondary scheme prioritizes requesting channels that have the...

Page 1225: ...equesting middle level channel If this level has no request the Scheduler continues to the low level If no requests occur the Scheduler truncates the seven state cycle and starts a new cycle at time s...

Page 1226: ...ime slot one of cycle C are passed to the middle level which is the next priority level after high Time slots two and three of cycle C are passed to the low level which contains the three remaining ch...

Page 1227: ...cycle B Cycle C has one of the low priority channels serviced before the second middle one Cycle D however no longer has the priority inversion In cycle B after the time slot 2 only a low priority req...

Page 1228: ...ndary scheme prioritizes these requests The Scheduler services channels on each of the three priority levels beginning with the lowest numbered channel on that level SLOT Number 6 7 1 2 4 4 5 7 4 6 4...

Page 1229: ...equesting service secondary scheme The Scheduler notes the still unserviced middle level channel and proceeds to time slot three 6 Time slot three is allocated for high priority The slot is allocated...

Page 1230: ...s is accessed which may lead to a lack of internal consistency if two or more related parameters are read when only part of them is updated eTPU provides mechanisms to guarantee parameter coherency Th...

Page 1231: ...of 2 words and the two parameters must be sequential The other area is the channel parameter area where the microcode normally accesses the parameters usually with the channel relative address mode s...

Page 1232: ...ost read the two parameters from the temporary area into Host memory registers 29 3 4 3 SDM Arbitration Up to four entities can access SDM two Microengines in a dual eTPU Engine system the Coherent Du...

Page 1233: ...ed Digital Filter EDF The EDF eliminates passing of signal transitions which are caused by noise Its purpose is to eliminate false transition service requests caused by noise pulses which are shorter...

Page 1234: ...e response to the first filter clock period in which the signal is continuously stable This may add to the latency and also to the minimum detected signal pulse in a noisy environment 29 3 4 4 4 Bypas...

Page 1235: ...es are out of phase by 1 eTPU clock even when Time Bases are shared between them through STAC 29 3 5 1 Timer Count Register 1 TCR1 TCR1 can be used in the following modes Internally Clocked Mode Exter...

Page 1236: ...starts counting up to TCR1P when etpu_gtbe_in is asserted When TCR1 increments etpu_gtbe_in 1 the prescaler starts a new count and the new TCR1P becomes effective When TCR1 is written by microcode th...

Page 1237: ...cked Modes TCR2 is driven by internal clock with count rate of eTPU clock divided by eight All clock sources pass through a prescaler In addition the TCR2 count can be originated from the EAC which is...

Page 1238: ...r ETPUTBCR In this mode the TCRCLK signal enables or disables transfer of the eTPU clock divided by 8 to the TCR2 prescaler By programming the prescaler TCR2 can run at rates from eTPU clock divided b...

Page 1239: ...ount Control and High Rate logic see the eTPU Reference Manual for details which provides the interpolated pin position and handle cases of missing tooth acceleration de acceleration and mechanical co...

Page 1240: ...nt or Angle STAC bus configuration is provided by the ETPUREDCR bits REN1 2 and RSC1 2 REN1 2 enable the STAC interface to interact with the resource either TCR1 or TCR2 bus RSC1 2 configure the resou...

Page 1241: ...hey are the same for both engines because the prescalers also freeze when etpu_gtbe_in 0 Microcode can always write to TCR1 2 registers with either value of etpu_gtbe_in NOTE The timebase prescalers a...

Page 1242: ...ontinuously restarting after the completion of each cycle when it sets the ETPUMCR register flag SCMMISC see Section 29 2 5 1 ETPUMCR eTPU Module Configuration Register The average time for a MISC cal...

Page 1243: ...ion and accumulator reset 29 3 7 Performance Monitoring Features 29 3 7 1 Idle Counter The Idle Counter Register ETPUIDLER see Section 29 2 7 2 ETPUIDLER eTPU Idle Register continuously counts microcy...

Page 1244: ...to eTPU transfers the microcode checks a flag set by the host indicating the existence of new parameter data in the TPA It can then either access TPA data directly or copy it to the PPA For eTPU to Ho...

Page 1245: ...ons use single action channels which have single transition and single match functionality They are not optimized for the eTPU hardware enhancement which support various double action modes These exam...

Page 1246: ...ls is independent This means that for example all 32 channel signals can change thread at the same moment provided that the function software sets up the channel hardware to do so beforehand With Host...

Page 1247: ...n any2 threads not counting initialization threads it is safe to say that the worst case latency shown in Figure 29 35 represents both the worst case high time and the worst case low time Notice in Fi...

Page 1248: ...is requesting service during a middle level time slot a high level channel is granted service or if no high level channel is requesting service a low level channel is granted service If no low level c...

Page 1249: ...RR set and SGR cleared the scheduler does not clear the SGR group and the requesting middle level channel is serviced on the next middle level time slot or possibly sooner by priority passing 29 4 2 3...

Page 1250: ...percentage gives a good RCR and CPCR The eTPU application provides a good estimation of CCR NOTE The programming practice of polling a flag in the eTPU SDM causes a very high RCR and should be avoided...

Page 1251: ...Each Active Channel A table for eTPU functions should list the longest threads not counting initialization threads for the functions and the number of eTPU SDM accesses in the longest thread semaphor...

Page 1252: ...the system configuration shown in Table 29 22 SPWM Mode 0 Mode1 Mode 2 14 18 20 no linking 22 linking 4 4 4 4 PMA 94 8 PMM 94 8 PSP Angle Angle Mode Angle Time Mode 76 50 6 3 SM 1 160 21 PPWA Mode 0...

Page 1253: ...M accesses 1 0 09 2 CPU clock waits 10 9 CPU clocks rounded up to 11 CPU clocks Channel 2 worst case service time 11 CPU clocks 2 Assume channel 0 has just been serviced and that channels 1 and 2 are...

Page 1254: ...e Figure 29 40 Figure 29 40 Next Servicing for Channel 1 Channel 0 will be serviced twice and channel 2 once before channel 1 is serviced again 3 Add time for the six clock CPU time slot transitions S...

Page 1255: ...d four times and channel 1 twice before channel 2 is serviced again 3 Add time for the ten clock CPU time slot transitions and the four clock NOPs See Figure 29 41 and Table 29 25 245 clocks 25 ns clo...

Page 1256: ...of request 2 If a function is active during system initialization but not during the high speed running mode of the system then that system does not need to be included in the high speed worst case la...

Page 1257: ...re periods of 5 kHz 200 ms period The CPU is interrupted by the channel running the PPWA function after measuring 200 periods every 40 ms The interrupt service routine performs an averaging of the per...

Page 1258: ...15 worst case service time 10 CPU clocks To find the WCL for channel 0 assume channel 0 has just finished service Map the channels in the H M H L H M H sequence See Figure 29 42 Figure 29 42 Worst Ca...

Page 1259: ...on with this system configuration the WCL for channels 2 and 8 is 4 7 ms which is within the 40 and 80 ms WCL requirements Table 29 27 Second Try System Configuration Channel Priority Function1 2 1 0...

Page 1260: ...MISC MISC right shifted by 1 bit MISC MISC XOR 0x80400007 else MISC MISC right shifted by 1 bit end if MISC MISC XOR RAM data The code example below shows an excerpt of C code that calculates the MISC...

Page 1261: ...re is calculated the Host CPU can be notified via Global Exception if the MISC Accumulator does not match the value in ETPUMISCCMPR The average time taken by MISC to complete the signature of the whol...

Page 1262: ...Enhanced Time Processing Unit eTPU2 29 94 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...

Page 1263: ...2 Features 22 Bit Address bus with transfer size indication 16 Bit Data bus 32 bit Data Bus in muxed mode Multiplexed Address on Data pins single master Memory controller with support for various mem...

Page 1264: ...e to arbitrate for the bus before starting each cycle The BR BG and BB signals are not used by the EBI in this mode and are Table 30 1 Device Specific Signal Naming Generic Signal Name Equivalent Chip...

Page 1265: ...r error internally no external D_TEA assertion 30 1 4 4 Slower Speed Modes In slower speed modes the external D_CLKOUT frequency is divided by 2 3 etc compared with that of the internal system bus The...

Page 1266: ...ete the address space e g D_ADD 8 15 are commonly present as non muxed address pins NOTE The EBI also drives the unused 16 D_ADD_DAT signals with the MSBs of the external address zero padded in front...

Page 1267: ...al pins used by the EBI Not all signals listed here are available external to the chip Refer to Table 30 1 and the Signals chapter for device specific signal naming and availability Table 30 2 Signal...

Page 1268: ...d by the master to indicate that this transaction is targeted for a particular memory bank on the Calibration external bus The calibration chip selects are driven only by the EBI External master acces...

Page 1269: ...ve their data output buffers off when D_OE is negated D_OE is only asserted for chip select accesses For read cycles D_OE is asserted one clock after D_TS assertion and held until the termination of t...

Page 1270: ...only D_WE 0 1 are used by the EBI regardless of which half of the D_ADD_DAT bus is selected via the D16_31 bit in the EBI_MCR See Section 30 4 1 11 Four Write Byte Enable D_WE Signals for more details...

Page 1271: ...ster 32 R 0x0000_0000 30 3 1 2 30 11 EBI_BASE 0xC EBI_BMCR EBI Bus Monitor Control Register 32 R W 0x0000_FF80 30 3 1 3 30 12 EBI_BASE 0x10 EBI_BASE 0x3C Reserved EBI_BASE 0x40 EBI_CAL_BR0 EBI Calibra...

Page 1272: ...nfiguration Register contains bits which configure various attributes associated with EBI operation Offset EBI_BASE 0 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0...

Page 1273: ...enable clk signal 26 28 Reserved 29 D16_31 Data Bus 16_31 Select The D16_31 bit controls whether the EBI uses the D_ADD_DAT 0 15 or D_ADD_DAT 16 31 signals when in 16 bit Data Bus Mode DBM 1 or for c...

Page 1274: ...s bit is set if the cycle was terminated by a bus monitor timeout 0 No error 1 Bus monitor timeout occurred Offset EBI_BASE 0xC Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0...

Page 1275: ...eserved Offset EBI_BASE 0x40 0x48 0x50 0x58 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R BA1 W RESET 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R...

Page 1276: ...the BL bit is ignored treated as 1 Note The EBI does NOT support a 2 word external burst length This means that neither a 4 beat burst to a 16 bit external memory nor a 2 beat burst to 32 bit externa...

Page 1277: ...d by an external device 30 BI Burst Inhibit This bit determines whether or not burst read accesses are allowed for this chip select bank The BI bit is ignored treated as 1 for chip select accesses wit...

Page 1278: ...Base Register BA field for more details 17 23 Reserved 24 27 SCY Cycle length in clocks This field represents the number of wait states external cycles inserted after the address phase in the single...

Page 1279: ...e Each CS bank is configured via its own pair of Base and Option Registers Each time an internal to external bus cycle access is requested the internal address is compared with the base address of eac...

Page 1280: ...of accesses that are not controlled by the chip selects is not supported for any other case besides the special case of 32 bit accesses in 16 bit data bus mode Burst writes are not supported for any o...

Page 1281: ...th up to 4 chip selects The EBI contains 4 calibration chip select signals controlling 4 independent memory banks on the external calibration bus See Section 30 4 2 10 Calibration Bus Operation for mo...

Page 1282: ...des for more details on this feature The timing diagrams for slower speed modes are identical to those for full speed mode except that the frequency of D_CLKOUT is reduced 30 4 1 13 Stop and Module Di...

Page 1283: ...ort for more details 30 4 1 16 Compatible with MPC5xx External Bus with some limitations The EBI is compatible with the external bus of the MPC5xx parts meaning that it supports most devices supported...

Page 1284: ...sfer of data from master to slave in write cycles or from slave to master on read cycles if any is to be transferred The data phase may transfer a single beat of data 1 4 bytes for non burst operation...

Page 1285: ...iagrams Figure 30 9 Basic Flow Diagram of a Single Beat Read Cycle Figure 30 10 Single Beat 32 bit Read Cycle CS Access Zero Wait States Yes No Receives Address Asserts Transfer Start D_TS Drives Addr...

Page 1286: ...at Write Flow The handshakes for a single beat write cycle are illustrated in the following flow and timing diagrams Wait state D_CLKOUT D_ADD 9 30 D_TS D_TA D_RD_WR D_BDIP D_OE CS n D_ADD_DAT is vali...

Page 1287: ...v 1 Figure 30 13 Basic Flow Diagram of a Single Beat Write Cycle Yes No Receives Address Asserts Transfer Start D_TS Drives Address Attributes Master Receives Data CS Access SETA Asserts Transfer Ackn...

Page 1288: ...le Beat 32 bit Write Cycle CS Access Zero Wait States Figure 30 15 Single Beat 32 bit Write Cycle CS Access One Wait State D_CLKOUT D_ADD 9 30 D_TS D_TA D_RD_WR D_BDIP CS n D_ADD_DAT is valid D_ADD_DA...

Page 1289: ...0 20 and Figure 30 21 Besides this dead cycle in most cases back to back accesses on the external bus do not cause any change in the timing from that shown in the previous diagrams and the two transac...

Page 1290: ...o Back 32 bit Reads to the Same CS Bank Figure 30 18 Back to Back 32 bit Reads to Different CS Banks D_ADD_DAT is valid D_ADD_DAT is valid D_CLKOUT D_ADD 9 30 D_TS D_TA D_RD_WR D_BDIP D_OE CS n D_ADD_...

Page 1291: ...9 Write After Read to the Same CS Bank Figure 30 20 Back to Back 32 bit Writes to the Same CS Bank D_ADD_DAT is valid D_ADD_DAT is valid D_CLKOUT D_ADD 9 30 D_TS D_TA D_RD_WR D_BDIP CSx D_ADD_DAT 0 31...

Page 1292: ...equiring the memory device to sequentially drive each word on the data bus The selected slave device must internally increment D_ADD 27 29 also D_ADD30 in the case of a 16 bit port size device of the...

Page 1293: ...a it asserts the D_BDIP signal Upon receiving the data prior to the last data the EBI negates D_BDIP Thus the slave stops driving new data after it receives the negation of D_BDIP on the rising edge o...

Page 1294: ...Basic Flow Diagram of a Burst Read Cycle No Yes Receives Address Asserts Transfer Start D_TS Drives Address Attributes Master Next to Last Data Beat Slave Drives Data Asserts Transfer Acknowledge D_T...

Page 1295: ...lt value of TBDIP 0 in the appropriate EBI Base Register results in D_BDIP being asserted SCY 1 cycles after the address transfer phase and being held asserted throughout the cycle regardless of the w...

Page 1296: ...shows an example of the TBDIP 1 timing for the same 4 beat burst shown in Figure 30 25 Figure 30 26 Burst 32 bit Read Cycle One Wait State between Beats TBDIP 1 D_ADD_DAT is valid Wait state Wait stat...

Page 1297: ...internal request These transfers have no additional dead cycles in between that are not present for back to back stand alone transfers except for the case of writes with an internal request size of 6...

Page 1298: ...evice using external D_TA requiring eight 32 bit external transactions Note that due to the use of external D_TA D_RD_WR does not toggle between the accesses unless that access is the end of a 64 bit...

Page 1299: ...asking out the lower 4 bits to fix them at zero Table 30 15 Examples of 4 word Burst Addresses 1st Address Lower 5 bits of 1st Address 0x10 no carry Final 2nd Address After Masking Lower 4 Bits 0x000...

Page 1300: ...16 bit port requiring four 16 bit external transactions Figure 30 30 Single Beat 64 bit Read Cycle 16 bit Port Size Basic Timing Expects more data D_CLKOUT D_ADD 9 30 D_BDIP D_TA D_RD_WR D_TS D_OE CS...

Page 1301: ...never have a misaligned external access from one to the other In the erroneous case that an externally initiated misaligned access does occur the EBI errors the access by asserting D_TEA externally a...

Page 1302: ...e not required during that read cycle Table 30 17 Data Bus Requirements for Read Cycles Transfer Size Address 32 Bit Port Size 16 Bit Port Size1 A30 A31 D0 D7 D8 D15 D16 D23 D24 D31 D0 D72 D8 D153 Byt...

Page 1303: ...drive the D_TA signal leaving it up to an external device or weak internal pullup to drive D_TA For EBI mastered chip select accesses when the SETA bit is 0 the EBI drives D_TA the entire cycle asser...

Page 1304: ...hip select accesses with SETA 0 a D_TEA assertion that occurs 1 cycle before or during the last D_TA of the access could be ignored by the EBI since it will have completed the access internally before...

Page 1305: ...also occur in a single master system if a non chip select 32 bit access to a 16 bit port is performed Figure 30 34 shows a 32 bit non chip select read from an external master in 16 bit data bus mode...

Page 1306: ...ibration chip selects to steer accesses to the calibration bus instead of the primary external bus Since the calibration bus has no arbitration signals the arbitration on the primary bus controls acce...

Page 1307: ...ion bus can similarly be derived from other figures in this document by replacing CS with CAL_CS Figure 30 36 Back to Back 32 bit Reads to CS CAL_CS Banks 30 4 2 11 Misaligned Access Support This sect...

Page 1308: ...trobe signals on AHB bus Shown with Big Endian byte ordering in this table even though internal master AHB bus uses Little Endian byte ordering EBI flips order internally HSIZE4 4 Internal signal on A...

Page 1309: ...0x9 000 1001 1 000 010 1011 0111 2 0 Half 0x3 0xB 000 100 1110 0111 1 010 100 1011 0111 3 0 Half 0x5 0xD 100 1001 1 100 110 1011 0111 4 0 Half 0x7 0xF 2 AHB transfers 1115 1110 000 0111 4 1 110 1011 0...

Page 1310: ...000 0000 12 1 1007 110 0011 0011 000 010 0011 0011 13 0 Doubleword 0x2 0xA 2 AHB transfers 000 100 1100 0000 000 0011 13 1 010 100 110 0011 0011 0011 000 0011 14 0 Doubleword 0x6 0xE 2 AHB transfers...

Page 1311: ...ch can be seen in Figure 30 37 Figure 30 37 Small access 32 bit read to 16 bit port on Address Data multiplexed bus 30 5 Initialization Application Information 30 5 1 Booting from External Memory The...

Page 1312: ..._CLKOUT D_TS and D_BDIP pins are not used by the memory and bursting is not supported However the EBI still drives these outputs and always drives and latches all signals at posedge D_CLKOUT i e there...

Page 1313: ...ronous Memories The connections to an asynchronous memory are the same as for a synchronous memory except that the D_CLKOUT D_TS and D_BDIP signals are not used Figure 30 39 shows a block diagram of a...

Page 1314: ...onous Memory Three Initial Wait States 30 5 4 Connecting an MCU to Multiple Memories The MCU can be connected to more than one memory at a time Figure 30 42 shows an example of how two memories could...

Page 1315: ...ache line rationale required for performance and compatibility with e200z core Removed these variable timing attributes from Option Register CSNT ACS TRLX EHTR rationale reduces tester edgesets and co...

Page 1316: ...DIP assertion is default behavior rationale unaware of any memories that require D_BDIP to assert earlier than LBDIP timing so reduce number of CS control bits and complexity Modified arbitration prot...

Page 1317: ...discussed in Section 31 10 e200z7 Class 3 Nexus Module NZ7C3 through Section 31 11 NZ7C3 Memory Map and Register Definition Nexus crossbar eDMA interface NXDM and Nexus FlexRay interface NXFR Refer to...

Page 1318: ...97 06 2 0 2 0 2 RU 13 X LOLDU 3RUW 972 7 3RUW RQWUROOHU 7 1 0B 1 5 XIIHU DFKH 5 3HULSKHUDO WHUQDO XV QWHUIDFH ULGJH 3HULSKHUDO ULGJH 65 0 ODVK 0 DFKH 1 0B XIIHU XIIHU XIIHU 038 5HVHUYHG XIIHU 1H XV H...

Page 1319: ...essaging OTM OTM facilitates ownership trace by providing visibility of which process ID or operating system task is activated An ownership trace message is transmitted when a new process task is acti...

Page 1320: ...ing method uses the branch predicate method to reduce the number of generated messages Watchpoint messaging via the auxiliary port WPM provides visibility of the occurrence of the eTPU s watchpoints a...

Page 1321: ...riting the configuration registers via the JTAG port The number of MDO pins available is 12 Unused MDO pins can be used as GPIO Details on GPIO functionality configuration can be found in Section 7 3...

Page 1322: ...ng OTM BTM DTM and other messages to the development tool The development tool must sample MDO on the rising edge of MCKO The width of the MDO bus used is determined by the Nexus PCR FPM configuration...

Page 1323: ...Data Input TDI The TDI pin receives serial test instruction and data TDI is sampled on the rising edge of TCK 31 2 1 10 Test Mode Select TMS The TMS pin is used to sequence the IEEE 1149 1 2001 TAP c...

Page 1324: ...Address 3 NZ7C3_DTEA3 21 e200z7 Data Trace End Address 4 NZ7C3_DTEA4 48 Development Status DS 50 Overrun Control OVCR 51 Watchpoint Mask WMSK 53 Program Trace Start Trigger Control PTSTC 54 Program T...

Page 1325: ...SC eTPU Engine 1 eTPU Engine 2 2 eTPU2 Development Control NDI_eTPU2_DC 4 eTPU2 Development Status NDEDI_eTPU2_DS 11 eTPU2 Watchpoint Trigger NDI_eTPU2_WT 13 eTPU2 Data Trace Control NDI_eTPU2_DTC 22...

Page 1326: ...mpare 2 IAC2 010 0010 Instruction Address Compare 3 IAC3 010 0011 Instruction Address Compare 4 IAC4 010 0100 Data Address Compare 1 DAC1 010 0101 Data Address Compare 2 DAC2 010 0110 Data Value Compa...

Page 1327: ...ontrol register 6 DBCR6 011 1000 011 1100 Invalid value do not access 011 1101 Debug Data Acquisition Message Register DDAM 011 1110 Debug Event Control DEVENT 011 1111 Debug External Resource Control...

Page 1328: ...nal cores BYPASS 11111 Bypass the TAP controller Table 31 5 Nexus Client JTAG Instructions Instruction Description Opcode NPC JTAG Instruction Opcodes NEXUS_ENABLE Opcode for NPC Nexus Enable instruct...

Page 1329: ...m operating frequency of the auxiliary port pins 31 4 4 Nexus Messaging Most of the messages transmitted by the NDI include a SRC field This field is used to identify which source generated the messag...

Page 1330: ...a development interface based on the IEEE ISTO 5001 2001 standard and must share the input and output ports that interface with the development tool The NPC controls the usage of these ports in a man...

Page 1331: ...registers accessible to the end user Individual bit level descriptions and reset states of the registers are included 31 6 1 Memory Map Table 31 9 shows the NPC registers by index values The register...

Page 1332: ...controller state machine and allows instructions to be loaded into the module to enable the NPC for register access NEXUS_ENABLE or select the bypass register as the shift path from TDI to TDO BYPASS...

Page 1333: ...e MCKO is enabled can produce unpredictable results Reg Index 0 Access User R O 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R Part Revision Number Design Center Part Identification Number W Reset 0 0 0 0 1...

Page 1334: ...es or disables MCKO clock gating If clock gating is enabled the MCKO clock is gated when the NPC is in enabled mode but not actively transmitting messages on the auxiliary output port When clock gatin...

Page 1335: ...port is found in Section 31 2 External Signal Description 31 7 2 1 Output Message Protocol The protocol for transmitting messages via the auxiliary port is accomplished with the MSEO functions The MSE...

Page 1336: ...ID message that the NPC can transmit on the auxiliary port The TCODE is the first packet transmitted Figure 31 6 shows the various message formats that the pin interface formatter has to encounter Ta...

Page 1337: ...ength packet it must start on a port boundary The field containing the TCODE number is always transferred out first followed by subsequent fields of information Within a field the lowest significant b...

Page 1338: ...ing with the least significant bit as illustrated in Figure 31 8 This applies for the instruction register and all Nexus tool mapped registers Figure 31 8 Shifting Data Into a Register 31 7 2 3 1 Enab...

Page 1339: ...LOGIC RESET RUN TEST IDLE SELECT DR SCAN SELECT IR SCAN CAPTURE DR CAPTURE IR SHIFT DR SHIFT IR EXIT1 DR EXIT1 IR PAUSE DR PAUSE IR EXIT2 DR EXIT2 IR UPDATE DR UPDATE IR 1 0 1 1 1 0 0 0 0 1 1 0 0 1 1...

Page 1340: ...and loaded in the UPDATE IR state At this point the Nexus controller state machine shown in Figure 31 10 transitions to the REG_SELECT state The Nexus controller has three states idle register select...

Page 1341: ...g a register the value is loaded from the IEEE 1149 1 2001 shifter to the register during the UPDATE DR state When reading a register there is no requirement to shift out the entire register contents...

Page 1342: ...31 7 2 6 MCKO MCKO is an output clock to the development tools used for the timing of MSEO and MDO pin functions MCKO is derived from the system clock and its frequency is determined by the value of...

Page 1343: ...controller with the NEXUS ENABLE instruction To write control data to NPC tool mapped registers the following sequence is required 1 Write the 7 bit register index and set the write bit to select the...

Page 1344: ...and read write access via the JTAG interface Reg Index 0 Access R O 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R PRN DC PIN W Reset 0 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 16 17 18 19 20 21 22 23 24 25 26 27 28 2...

Page 1345: ...hapter describes an NPC with a dedicated auxiliary port The auxiliary port is fully described in Section 31 2 External Signal Description 31 10 2 Block Diagram Figure 31 13 e200z7 Nexus3 Functional Bl...

Page 1346: ...tem This can include DRM and or DWM JTAG Compliant Device complying to IEEE 1149 1 JTAG standard JTAG IR DR Sequence JTAG instruction register IR scan to load an opcode value for selecting a developme...

Page 1347: ...of program and or data trace messaging High speed data input output via the auxiliary port Auxiliary interface for higher data input output Configurable minimum and maximum message data out pins One...

Page 1348: ...8 STATUS Fixed Development status register DS 31 24 Ownership Trace Message 6 6 TCODE Fixed TCODE number 2 0x02 4 4 SRC Fixed Source processor identifier 32 32 PROCESS Fixed Task Process ID tag Progr...

Page 1349: ...e Indirect Branch Message w Sync1 6 6 TCODE Fixed TCODE number 12 0x0C 4 4 SRC Fixed Source processor identifier 1 8 I CNT Variable Number of sequential instructions executed since last taken branch 1...

Page 1350: ...redicate instruction history see Section 31 13 1 Branch Trace Messaging BTM Program Trace Indirect Branch History Message w Sync 6 6 TCODE Fixed TCODE number 29 0x1D see footnote 1 below 4 4 SRC Fixed...

Page 1351: ...chpoint overrun 01001 10111 Invalid value 11000 BTM lost due to collision w higher priority message 11001 11111 Invalid value Table 31 20 RCODE values TCODE 27 Resource Code RCODE Description Resource...

Page 1352: ...JTAG OnCE port in compliance with IEEE 1149 1 NOTE Nexus 3 registers and output signals are numbered using bit 0 as the least significant bit This bit ordering is consistent with the ordering defined...

Page 1353: ...0x24 0x25 Data Trace End Address 2 DTEA2 0x13 R W 0x26 0x27 Data Trace End Address 3 DTEA3 0x14 R W 0x28 0x29 Data Trace End Address 4 DTEA4 0x15 R W 0x2A 0x2B Reserved 0x16 0x2F 0x28 0x5E 0x29 0x5F...

Page 1354: ...des a macroscopic view such as task flow reconstruction when debugging software written in a high level or object oriented language It offers the highest level of abstraction for tracking operating sy...

Page 1355: ...to enter the queue while the FIFO is emptying then the error message incorporates error encoding 01000 NOTE The OVC bits within the DC1 register can be set to delay the CPU to alleviate but not elimin...

Page 1356: ...branch that was taken Exception with the unique portion of the branch target address or exception vector address History field in the branch and predicate instructions that can generate the following...

Page 1357: ...bits which are both reported as consecutive bits in the history field Branch history messages solve predicated instruction tracking and save bandwidth since only indirect branches cause messages to be...

Page 1358: ...Indirect branches include all taken branches whose destination is determined at run time interrupts and exceptions If DC PTM is set indirect branch information is messaged out in the following format...

Page 1359: ...urce full message This information can be concatenated by the tool with the branch predicate history information from subsequent messages to obtain the complete branch history for a message The intern...

Page 1360: ...essage attempts to enter the queue while it is being emptied the error message incorporates the program trace only error encoding 00001 If both OTM and program trace messages attempt to enter the queu...

Page 1361: ...or an ownership trace message If the NZ7C3 module is enabled at reset a EVTI assertion initiates a program trace direct indirect branch with sync message if program trace is enabled upon the first dir...

Page 1362: ...initiates a direct indirect branch with sync message upon the next direct indirect branch if program trace is enabled and the EIC bits of the DC1 register have enabled this feature Sequential Instruc...

Page 1363: ...rect branch execution used for reconstructing the program flow This packet is implemented as a left shifting shift register The register is always pre loaded with a value of one 1 This bit acts as a s...

Page 1364: ...ion counter overflows when its value reaches 255 The next BTM message is converted to a synchronization type message 31 14 5 Program Trace Queueing NZ7C3 implements a message queue Messages that enter...

Page 1365: ...all data access that meet the selected range and attributes NOTE Data trace is only performed on the e200z7 virtual data bus This allows for data visibility for the incorporated data cache Only e200z...

Page 1366: ...leword access and sends out as a single data trace message with a single 64 bit data value 31 14 6 2 3 DTM Overflow Error Messages An error message occurs when the next message is denied service becau...

Page 1367: ...e EIC bits of the DC1 register have enabled this feature Upon data trace write read after the previous DTM message was lost due to an attempted access to a secure memory location Upon data trace write...

Page 1368: ...ace message is converted to a data write read with sync message Queue Overrun An error message occurs when a new message cannot be queued due to a full message queue The FIFO discards messages until i...

Page 1369: ...the original access a word and one with a size encoding for the portion which crossed the boundary 3 bytes NOTE An STM to the cache s store buffer within the data trace range initiates a DTM message I...

Page 1370: ...ned by the IEEE ISTO 5001 2011 standard NZ7C3 is not compliant with Class4 breakpoint watchpoint requirements defined in the standard The breakpoint watchpoint control register is not implemented MCKO...

Page 1371: ...nt Error Message An error message occurs when a new message cannot be queued due to the message queue being full The FIFO discards messages until it has completely emptied the queue After it is emptie...

Page 1372: ...bus with multiple configurable priority levels Memory mapped registers and other non cached memory can be accessed via the standard memory map settings All accesses are setup and initiated by the rea...

Page 1373: ...te data 4 The NZ7C3 module then arbitrates for the system bus and transfer the data value from the data buffer RWD register to the memory mapped address in the read write access address register RWA W...

Page 1374: ...e length of the burst and the number from the CNT field is decremented 5 When the entire burst transfer has completed without error ERR 0 NZ7C3 then asserts the RDY pin and the DV bit within the RWCS...

Page 1375: ...sserts the RDY pin This indicates that the device is ready for the next access 3 The data can then be read from the read write access data register RWD through the access method outlined in Section 31...

Page 1376: ...re defined for sequences of the read write protocol that differ from those described in the above sections 1 If the AC bit in the RWCS register is set to start read write accesses and invalid values a...

Page 1377: ...a write message with 12 MDO and two MSEO configuration T0 A0 D0 are the least significant bits LSB where Tx TCODE number fixed Sx Source processor fixed Table 31 30 Indirect Branch Message Example 12...

Page 1378: ...acket End Message Table 31 33 Accessing Internal Nexus3 Registers via JTAG OnCE Step TMS Pin Description 1 1 IDLE SELECT DR_SCAN 2 0 SELECT DR_SCAN CAPTURE DR Nexus command register value loaded in sh...

Page 1379: ...rm All output messages and register accesses are compliant with the protocol defined in the IEEE ISTO 5001 standard Table 31 34 Accessing Memory Mapped Resources Reads Step TCLK clocks Description 1 1...

Page 1380: ...f the NXFR is the same Figure 31 41 NXDM and NXFR Block Diagram 31 15 2 Features Features include the following Data trace via data write messaging DWM and data read messaging DRM This provides the ca...

Page 1381: ...s sharing the port 31 17 NXDM and NXFR Programmers Model This section describes the programmers model Nexus registers are accessed using the JTAG port in compliance with IEEE 1149 1 Refer to Chapter 3...

Page 1382: ...0x3F 0x40 0x7E 0x41 0x7F 1 The CSC and PCR registers are shown in this table as part of the Nexus programmer s model They are only present at the top level Nexus3 controller NPC not in the NXDM or NXF...

Page 1383: ...ed for future functionality 17 POTD Periodic Ownership Trace Disable 0 Periodic ownership trace message events are enabled 1 Periodic ownership trace message events are disabled 18 19 TSEN Timestamp E...

Page 1384: ...27 28 29 30 31 R EWC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 31 44 Development Control Register 2 DC2 Table 31 38...

Page 1385: ...Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 DTS DTE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 1386: ...es generated X1 Enable data read trace 1X Enable data write trace 4 23 Reserved read as 0 24 RC1 Range control 1 0 Condition trace on address within range endpoints inclusive 1 Condition trace on addr...

Page 1387: ...traced 31 17 2 6 Breakpoint Watchpoint Control Register 1 BWC1 Breakpoint watchpoint control register 1 controls attributes for generation of NXDM and NXFR watchpoint number 1 Access R W 0 1 2 3 4 5...

Page 1388: ...nt watchpoint 1 register compare 00 No register compare same as BWC1 31 30 2 b00 01 Invalid value 10 Compare with BWA1 value 11 Invalid value 15 BWT1 Breakpoint watchpoint 1 type 0 Invalid value 1 Wat...

Page 1389: ...ol 31 17 2 11 IEEE 1149 1 JTAG Test Access Port The NXDM and NXFR modules uses the IEEE 1149 1 TAP controller for accessing Nexus resources The JTAG signals themselves are shared by all TAP controller...

Page 1390: ...Access via JTAG Access to Nexus register resources is enabled by loading a single instruction NEXUS_ACCESS into the JTAG Instruction Register IR This IR is part of the IEEE 1149 1 TAP controller with...

Page 1391: ...nctional Description 31 17 4 Enabling NXDM and NXFR Operation The NXDM and NXFR module is enabled by loading a single instruction ACCESS_AUX_TAP_DMA or ACCESS_AUX_TAP_NXFR as shown in Table 31 4 into...

Page 1392: ...number 6 4 4 SRC Fixed Source processor identifier multiple Nexus configuration 3 3 DSZ Fixed Data size refer to Table 31 48 1 32 U ADDR Variable Unique portion of the data read value 1 64 DATA Variab...

Page 1393: ...0010 Data Trace overrun 00011 Invalid value 00100 Invalid value 00101 Invalid access opcode Nexus Register unimplemented 00110 Watchpoint overrun 00111 Invalid value 01000 Data Trace and Watchpoint ov...

Page 1394: ...write and data read messages contain the data write read value and the address of the write read access relative to the previous data trace message Data write message and data read message information...

Page 1395: ...message is a synchronization message if the eic bits of the dc register have enabled this feature Upon data trace write read after the previous dtm message was lost due to an attempted access to a sec...

Page 1396: ...FIFO discards messages until it has completely emptied the queue After it is emptied an error message is queued The error encoding indicates the types of messages that attempted to be queued while the...

Page 1397: ...M channel Data trace windowing is achieved via the address range defined by the DTEA and DTSA registers and by the RC1 2 field in the DTC All eDMA or FlexRay initiated read write accesses that fall in...

Page 1398: ...ing full The FIFO discards messages until it has completely emptied the queue After it is emptied an error message is queued The error encoding indicates which types of messages attempted to be queued...

Page 1399: ...Nexus Development Interface NDI Freescale Semiconductor 31 83 PXR40 Microcontroller Reference Manual Rev 1...

Page 1400: ...Nexus Development Interface NDI 31 84 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...

Page 1401: ...e select TMS and test clock input TCK TDI TDO TMS and TCK are compliant with the IEEE 1149 1 2001 standard and are shared with the NDI through the test access port TAP interface 32 1 1 Block Diagram F...

Page 1402: ...the operation of the data registers instruction register and associated circuitry 32 1 4 Modes of Operation The JTAGC uses JCOMP and a power on reset indication as its primary reset signals Several IE...

Page 1403: ...used to provide a minimum length serial path to shift data between TDI and TDO 32 1 4 4 TAP Sharing Mode The selectable auxiliary TAP controllers that share the TAP with the JTAGC are Nexus port cont...

Page 1404: ...e TAP controller is in the Shift IR state and latched on the falling edge of TCK in the Update IR state The latched instruction value can only be changed in the update IR and test logic reset TAP cont...

Page 1405: ...path from TDI to TDO selected when the ENABLE_CENSOR_CTRL instruction is active The default reset value of the CENSOR_CTRL register is 64 b0 The CENSOR_CTRL register transfers its value to a parallel...

Page 1406: ...oller is forced into the test logic reset state thus disabling the test logic and allowing normal operation of the on chip system logic In addition the instruction register is loaded with the IDCODE i...

Page 1407: ...terprets the sequence of logical values on the TMS pin Figure 32 5 shows the machine s states The value shown next to each state is the value of the TMS signal sampled on the rising edge of the TCK si...

Page 1408: ...chine Test logic reset Run test idle Select DR scan Select IR scan Capture DR Capture IR Shift DR Shift IR Exit1 DR Exit1 IR Pause DR Pause IR Exit2 DR Exit2 IR Update DR Update IR 1 0 1 1 1 0 0 0 0 1...

Page 1409: ...standard for more details The JTAGC implements the IEEE 1149 1 2001 defined instructions listed in Table 32 3 Table 32 3 JTAG Instructions Instruction Code 4 0 Instruction Summary IDCODE 00001 Selects...

Page 1410: ...of signals driven from MCU pins to be determined from the boundary scan register while the bypass register is selected as the serial path between TDI and TDO CLAMP enhances test efficiency by reducin...

Page 1411: ...SAMPLE instruction is active The sampled data is viewed by shifting it through the boundary scan register to the TDO output during the Shift DR state There is no defined action in the update DR state...

Page 1412: ...TDI and TDO when the EXTEST SAMPLE or SAMPLE PRELOAD instructions are loaded The shift register chain contains a serial input and serial output as well as clock and control signals 32 5 Initialization...

Page 1413: ...ible performance from the PXR40 It provides a description of the areas that should be focused on when optimizing an application for performance by describing the features and recommending settings to...

Page 1414: ...solve branch instructions and improve the accuracy of branch predictions the e200z7 core implements a dynamic branch prediction mechanism using a branch target buffer BTB a fully associative address c...

Page 1415: ...at BTB hits are not affected by the settings of this field Note that for branches with AA 1 the MSB of the displacement field is still used to indicate forward backward even though the branch is absol...

Page 1416: ...increases that system performance does not scale linearly Take care to ensure that the correct internal and or external Flash configuration is chosen for the selected system frequency The specific fl...

Page 1417: ...te concurrently with multiple slaves In order to maximize data throughput it is essential to keep arbitration delays to a minimum The configuration of the crossbar can have implications for the perfor...

Page 1418: ...unless the application can guarantee that coherency is maintained between multiple masters Consider locking the stack within the data cache Copyback mode in the cache generally uses fewer system resou...

Page 1419: ...ache invalidate 1 Cache invalidation operation When written to a 1 a cache invalidation operation is initiated by hardware Once complete this bit is reset to 0 Writing a 1 while an invalidation operat...

Page 1420: ...Descriptions Field Description 0 3 WID Way Instruction Disable 4 7 WDD Way Data Disables 8 10 Reserved 11 DCWM Data Cache Write Mode 12 13 DCWA Data Cache Write Allocation Policy 14 Reserved 15 DCECE...

Page 1421: ...ache Operation Aborted Indicates a Cache Invalidate or a Cache Lock Bits Flash Clear operation was aborted prior to completion This bit is set by hardware on an aborted condition and will remain set u...

Page 1422: ...uration registers 33 4 Application Software 33 4 1 Compiler Optimizations The most significant opportunity for influencing the performance of a given application is by compiler and linker optimization...

Page 1423: ...of an application Figure 33 5 Influence of Compiler Settings on Application Performance and Code Size NOTE Data measured using Dhrystone version 2 1 run on a Power Architecture based Powertrain devic...

Page 1424: ...and Discrete Fourier Transforms DFT A more general benefit of the SPE instruction set is the ability to load store 64 bits of data in single instruction Thus highly load store intensive functions make...

Page 1425: ...the VLE variable length encoding APU providing improved code density The VLE APU can be viewed as a supplement to the existing Power Architecture instruction set that can be conditionally applied to a...

Page 1426: ...with BUCSR BPEN Flush and enable to improve accuracy of branch predictions Branch Prediction BUCSR BPRED BUCSR BALLOC Consider fine tuning of BTB operation for specific applications System Frequency...

Page 1427: ...to move data where possible Most peripherals can generate eDMA requests to shift data Use the eDMAs to control movement of commands and results from ADC and to maintain circular buffers in system mem...

Page 1428: ...to absolute temperature This voltage VTSENS T is read by software using the on board eQADC module and used with the bandgap voltage and constants stored in flash memory during factory test to calculat...

Page 1429: ...Microcontroller Reference Manual Rev 1 Temperature Sensor Freescale Semiconductor 34 2 Figure 34 1 Calibration Points T JUNCTION VBG TLOW THIGH T JUNCTION VTSENS VBG TLOW TLOW THIGH VTSENS TLOW VTSENS...

Page 1430: ...ature factory calibration These values are stored in shadow flash memory during factory calibration See Section 34 3 6 1 Temperature Calculation Constants Register 0 for details VBG_CODE TLOW TTSENS_C...

Page 1431: ...e voltage from eQADC_A channel 145 ADC0 34 3 6 Registers The calibration constants described previously i e TLOW THIGH TSENS_CODE TLOW TSENS_CODE THIGH and VBG_CODE TLOW are stored in device shadow fl...

Page 1432: ...nd converted by the eQADC during factory test with device at hot temperature THIGH This is the TSENS_CODE THIGH parameter value referenced in the temperature calculation formula see Figure 34 2 16 17...

Page 1433: ...34 2 Temperature Calculation Constants Register 1 Field Descriptions Field Description 0 1 Reserved 2 15 TSCV3 Bandgap voltage sampled and converted by ADC during factory test This is the VBG_CODE TLO...

Page 1434: ...nt A 1 Revisions This appendix describes corrections to the PXR40 Microcontroller Reference Manual PXR40RM For convenience the corrections are grouped by revision Since this is the first revision of t...

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