Freescale Semiconductor PXR4030, Reference Manual

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Nexus Development Interface (NDI)
Freescale Semiconductor 31-69
PXR40 Microcontroller Reference Manual, Rev. 1
31.17.2.2 Watchpoint Trigger Register (WT)
The watchpoint trigger register allows the watchpoints defined internally to the NXDM and NXFR
modules to trigger actions. These watchpoints can control data trace enable and disable. The WT bits can
be used to produce an address related window for triggering trace messages.
NOTE
The WT bits ONLY enable data trace if the tm bits within the development
control register (DC) have not already been set to enable data trace.
31.17.2.3 Data Trace Control Register (DTC)
The data trace control register controls whether DTM Messages are restricted to reads, writes or both for
a user programmable address range. There are two data trace channels controlled by the DTC for the
NXDM and NXFR modules.
Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0
DTS DTE
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 31-45. Watchpoint Trigger Register (WT)
Table 31-39. WT Field Description
Field Description
0–5 Reserved, read as 0.
6–8
DTS
DTS - Data trace start control
000 Trigger disabled
001–100 Invalid value
101 Use internal watchpoint #1 (BWA1 register)
110 Use internal watchpoint #2 (BWA2 register)
111 Invalid value
9–11
DTE
DTE - Data trace end control
000 Trigger disabled
001–100 Invalid value
101 Use internal watchpoint #1 (BWA1 register)
110 Use internal watchpoint #2 (BWA2 register)
111 Invalid value
12–31 Reserved, read as 0.
Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
RWT1 RWT2
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RC1 RC2
0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 31-46. Data Trace Control Register (DTC)