Freescale Semiconductor PXR4030, Reference Manual

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Resets
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 4-7
the clock count finishes, the reset configuration pins are sampled. The reset controller then waits 4 clock
cycles before negating RSTOUT, and the associated bits/fields are updated in the SIU_RSR. In addition,
the LLRS bit is set, and all other reset status bits in the SIU_RSR are cleared. Refer to
Section 6.4.3.1, PLL
Lock Detection , in the FMPLL chapter for more information on loss of lock.
4.5.4 Loss of Clock
A Loss of Clock Reset occurs when a failure in either the reference signal or FMPLL output, and the Loss
of Clock Reset Enable (LOCRE) bit in the ESYNCR2 is set. The internal reset signal and RSTOUT pin
are asserted. The value on the WKPCFG and PLLCFG pins are applied at the assertion of the internal reset
signal (assertion of RSTOUT). Once the Loss of Clock and Loss of Lock reset request signals are negated,
the reset controller waits for a predetermined number of clock cycles (refer to
Section 4.3.2, RSTOUT ).
Once the clock count finishes, the reset configuration pins are sampled. The reset controller then waits 4
clock cycles before negating RSTOUT, and the associated bits/fields are updated in the SIU_RSR. In
addition, the LCRS bit is set, and all other reset status bits in the SIU_RSR are cleared. Refer to
Section 6.4.3.2, Loss-of-Clock Detection , in the FMPLL chapter for more information on loss of clock.
4.5.5 Core Watchdog Timer/Debug Reset
There are two watchdog timer resets: A core watchdog and a platform watchdog.
A Core Watchdog Timer Reset occurs when the e200z7 core watchdog timer is enabled (the e200z7 core
watchdog is counting core clocks, which is different than the peripheral/platform clocks), and a time-out
occurs with the Enable Next Watchdog Timer (EWT) and Watchdog Timer Interrupt Status (WIS) bits set
in the Timer Status Register, and with the Watchdog Reset Control (WRC) field in the Timer Control
Register configured for a reset. The WDRS bit in the SIU_RSR is also set when a debug reset command
is issued from a debug tool. To determine whether the WDRS bit was set due to a Watchdog Timer or
Debug Reset, see the WRS field in the e200z7 core Timer Status Register.
The effect of a Watchdog Timer or Debug Reset request is the same for the reset controller. The internal
reset signal and RSTOUT pin are asserted. The value on the WKPCFG pin is applied at the assertion of
the internal reset signal (assertion of RSTOUT), as is the PLLREF value. Once the Watchdog Timer/Debug
reset request is negated and the FMPLL Loss of Lock reset request signal is negated, the reset controller
waits for a predetermined number of clock cycles (refer to
Section 4.3.2, RSTOUT ). Once the clock count
finishes the reset configuration pins are sampled. The reset controller then waits 4 clock cycles before
negating RSTOUT, and the associated bits/fields are updated in the SIU_RSR. In addition, the WTRS bit
is set, and all other reset status bits in the SIU_RSR are cleared.
Refer to the e200z7 Core Reference Manual for more information on the core watchdog timer and debug
operation. Refer to Chapter 18, Software Watchdog Timer (SWT) , for more information on the platform
watchdog.
4.5.6 JTAG Reset
A system reset occurs when JTAG is enabled and either the EXTEST, CLAMP, or HIGHZ instructions are
executed by the JTAG controller. The internal reset signal is asserted. The state of the RSTOUT pin is
determined by the JTAG instruction. The values on the WKPCFG and PLLCFG pins are applied at the