Freescale Semiconductor PXR4030, Reference Manual

Page: 406 / 1434

Core (e200z7) Overview
PXR40 Microcontroller Reference Manual, Rev. 1
13-18 Freescale Semiconductor
The MAS3 register is shown below.
Table 13-8. MAS2 - EPN and Page Attributes
Field Comments, or Function when Set
0–21
EPN
Effective page number [0:21]
22–25 Reserved
1
26
VLE
PowerPC VLE
0 This page is a standard BookE page
1 This page is a PowerPC VLE page
27
W
Write-through Required
0 This page is considered write-back with respect to the caches in the system
1 All stores performed to this page are written through to main memory
28
I
Cache Inhibited
0 This page is considered cacheable
1 This page is considered cache-inhibited
29
M
Memory Coherence Required
0 Memory Coherence is not required
1 Memory Coherence is required
30
G
Guarded
0 Access to this page are not guarded, and can be performed before it is known
if they are required by the sequential execution model
1 All loads and stores to this page are performed without speculation (i.e. they are
known to be required)
PXR40 uses the guarded attribute as described in the e200z759n3 reference
manual’s Page Table Control Bits section.
31
E
Endianness
0 The page is accessed in big-endian byte order.
1 The page is accessed in true little-endian byte order.
1
These bits are not implemented, will be read as zero, and writes are ignored.
RPN
U
0
U
1
U
2
U
3
U
X S
X U
W
S
W
U
R S
R
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SPR - 627; Read/ Write; Reset - Unaffected
Figure 13-10. MMU Assist Register 3 (MAS3)