Freescale Semiconductor PXR4030, Reference Manual

Page: 1419 / 1434

Device Performance Optimization
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 33-7
16
ICEI Instruction Cache Error Injection Enable
17 Reserved
18–19
ICEDT Instruction Cache Error Detection Type
20 Reserved
21
ICUL Instruction Cache Unable to Lock
22
ICLO Instruction Cache Lock Overflow
23
ICLFC Instruction Cache Lock Bits Flash Clear
24
ICLOA Instruction Cache Lock Overflow Allocate
25–26
ICEA Instruction Cache Error Action
27–28 Reserved
29
ICABT Instruction Cache Operation Aborted
Indicates a Cache Invalidate or a Cache Lock Bits Flash Clear operation was aborted prior to completion. This
bit is set by hardware on an aborted condition, and will remain set until cleared by software writing 0 to this bit
location.
30
ICINV Instruction Cache Invalidate
0 - No cache invalidate
1 - Cache invalidation operation
When written to a ‘1’, a cache invalidation operation is initiated by hardware. Once complete, this bit is reset to
‘0’. Writing a ‘1’ while an invalidation operation is in progress will result in an undefined operation. Writing a ‘0’ to
this bit while an invalidation operation is in progress will be ignored. Cache invalidation operations require
approximately 36 cycles to complete. Invalidation occurs regardless of the enable (ICE) value.
During cache invalidations, the parity check bits are written with a value dependent on the ICEDT selection.
ICEDT should be written with the desired value for subsequent cache operation when ICINV is set to ‘1’ for proper
operation of the cache.
31
ICE Instruction Cache Enable
0 - Cache is disabled
1 - Cache is enabled
When disabled, cache lookups are not performed for instruction accesses.
Other L1CSR0 cache control operations are still available.
Table 33-2. L1CSR1 Register Field Descriptions (continued)
Field Description