Power Management Controller (PMC)
Freescale Semiconductor
5-13
PXR40 Microcontroller Reference Manual, Rev. 1
17
LVFCH
VDDEH LVF clear. This write-only bit is used to clear the low-voltage flag associated with the monitored
VDDEH supplies. Writing 1 to this bit clears LVFH. Writing 0 has no effect. Reading this bit always return 0.
0 No effect.
1 Clears LVFH.
18
LVFC50
VDDREG LVF clear. This write-only bit is used to clear the low-voltage flag associated with the VDDREG
voltage regulator supply. Writing 1 to this bit clears LVF50. Writing 0 has no effect. Reading this bit always
returns 0.
0 No effect.
1 Clears LVF50.
19
LVFC33
VDDSYN LVF clear. This write-only bit is used to clear the low-voltage flag associated with the VDDSYN 3.3
V supply. Writing 1 to this bit clears LVF33. Writing 0 has no effect. Reading this bit always returns 0.
0 No effect.
1 Clears LVF33.
20
LVFCC
Core-voltage-supply LVF clear. This write-only bit is used to clear the low-voltage flag associated with the
core voltage supply. Writing 1 to this bit clears LVFC. Writing 0 has no effect. Reading this bit always returns
0.
0 No effect.
1 Clears LVFC.
21
LVFCA
VDDA LVF clear. This write-only bit is used to clear the low-voltage flag associated with the analog power
input VDDA1. Writing 1 to this bit clears LVFA. Writing 0 has no effect. Reading this bit always return 0.
0 No effect.
1 Clears LVFA.
22–23
Reserved
24
LVFR
Reset-pin-supply low-voltage flag. This read-only bit is the low-voltage flag associated with the supply of the
I/O segment that contains the reset pin. It is asserted when the supply falls below the corresponding LVD
threshold, and can be cleared by the CPU by writing 1 to the LVFCR bit. If the LVIER bit is also asserted, a
low-voltage interrupt is sent to the CPU. If LVRER is also asserted, a system reset will be generated, which
will clear LVFR and negate the interrupt request.
0 No occurrence.
1 LVD occurrence detected on the supply of the I/O segment that contains the reset pin.
25
LVFH
VDDEH low-voltage flag. This read-only bit is the low-voltage flag associated with the monitored VDDEH
supplies. It is asserted when any monitored VDDEH supply falls below its corresponding LVD threshold, and
can be cleared by the CPU by writing 1 to the LVFCH bit. If the LVIEH bit is also asserted, a low-voltage
interrupt is sent to the CPU. If LVREH is also asserted, a system reset will be generated, which will clear
LVFH and negate the interrupt request.
0 No occurrence.
1 LVD occurrence detected on a monitored VDDEH supply.
26
LVF50
VDDREG low-voltage flag. This read-only bit is the low-voltage flag associated with the VDDREG supply of
the voltage regulator. It can be cleared by the CPU by writing 1 to the LVFC50 bit. If the LVIE5 bit is also
asserted, a low-voltage interrupt is sent to the CPU. If LVRE50 is also asserted, a system reset will be
generated, which will clear LVF50 and negate the interrupt request.
0 No occurrence.
1 LVD occurrence detected on the VDDREG supply of the voltage regulator.
Table 5-6. PMC_SR Field Descriptions (continued)
Field
Description
Summary of Contents for PXR4030
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