Freescale Semiconductor PXR4030, Reference Manual

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Core (e200z7) Overview
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 13-25
Table 13-13. Machine Check Syndrome Register (MCSR)
Field Description
Exception
Type
1
Recoverable
0
MCP
Machine check input pin Async Mchk Maybe
1
IC_DPERR
Instruction Cache data array parity error Async Mchk Precise
2
CP_PERR
Data Cache push parity error Async Mchk Unlikely
3
DC_DPERR
Data Cache data array parity error Async Mchk Maybe
4
EXCP_ERR
ISI, ITLB, or Bus Error on first instruction fetch for an
exception handler Async Mchk Precise
5
IC_TPERR
Instruction Cache Tag parity error Async Mchk Precise
6
DC_TPERR
Data Cache Tag parity error Async Mchk Maybe
7
IC_LKERR
Instruction Cache Lock error
Indicates a cache control operation or invalidation
operation invalidated one or more locked lines in the
Icache or encountered an uncorrectable lock error, or
that an Icache miss with an uncorrectable lock error
occurred. May also be set on locked line refill error. Status —
8
DC_LKERR
Data Cache Lock error
Indicates a cache control operation or invalidation
operation invalidated one or more locked lines in the
Dcache or encountered an uncorrectable lock error, or
that an Icache miss with an uncorrectable lock error
occurred. May also be set on locked line refill error. Status —
9–10 Reserved, should be cleared. —
11
NMI
NMI input pin NMI —
12
MAV
MCAR Address Valid
Indicates that the address contained in the MCAR was
updated by hardware to correspond to the first detected
Async Mchk error condition Status —
13
MEA
MCAR holds Effective Address
If MAV=1,MEA=1 indicates that the MCAR contains an
effective address and MEA=0 indicates that the MCAR
contains a physical address Status —
14 Reserved, should be cleared. —
15
IF
Instruction Fetch Error Report
An error occurred during the attempt to fetch an
instruction. This could be due to a parity error, or an
external bus error. MCSRR0 contains the instruction
address. Error
Report Precise