Error Correction Status Module (ECSM)
17-8
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
for the ECC error generation register definition.
Offset: ECSM_BAS 0x004A
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
0
FRC1BI FR11BI
0
0
FRCNCI FR1NCI
0
ERRBIT
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 17-4. ECC Error Generation (ECSM_EEGR) Register
Table 17-6. ECSM_EEGR Field Descriptions
Field
Description
0–1
Reserved
2
FRC1BI
Force RAM Continuous 1-Bit Data Inversions. The assertion of this bit forces the RAM controller to create 1-bit data
inversions, as defined by the bit position specified in ERRBIT, continuously on every write operation.
The normal ECC generation takes place in the RAM controller, but then the polarity of the bit position defined by
ERRBIT is inverted to introduce a 1-bit ECC event in the RAM.
After this bit has been enabled to generate another continuous 1-bit data inversion, it must be cleared before being
set again to properly re-enable the error generation logic.
0 No RAM continuous 1-bit data inversions are generated.
1 1-bit data inversions in the RAM are continuously generated.
3
FR11BI
Force RAM One 1-bit Data Inversion. The assertion of this bit forces the RAM controller to create one 1-bit data
inversion, as defined by the bit position specified in ERRBIT, on the first write operation after this bit is set.
The normal ECC generation takes place in the RAM controller, but then the polarity of the bit position defined by
ERRBIT is inverted to introduce a 1-bit ECC event in the RAM.
After this bit has been enabled to generate a single 1-bit data inversion, it must be cleared before being set again
to properly re-enable the error generation logic.
0 No RAM single 1-bit data inversion is generated.
1 One 1-bit data inversion in the RAM is generated.
4–5
Reserved
6
FRCNCI
Force RAM Continuous Noncorrectable Data Inversions. The assertion of this bit forces the RAM controller to create
2-bit data inversions, as defined by the bit position specified in ERRBIT and the overall odd parity bit, continuously
on every write operation.
After this bit has been enabled to generate another continuous noncorrectable data inversion, it must be cleared
before being set again to properly re-enable the error generation logic.
The normal ECC generation takes place in the RAM controller, but then the polarity of the bit position defined by
ERRBIT and the overall odd parity bit are inverted to introduce a 2-bit ECC error in the RAM.
0 No RAM continuous 2-bit data inversions are generated.
1 2-bit data inversions in the RAM are continuously generated.
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
Page 30: ...PXR40 Microcontroller Reference Manual Rev 1 Freescale Semiconductor xxx...
Page 40: ...PXR40 Microcontroller Reference Manual Rev 1 xl Freescale Semiconductor...
Page 66: ...Memory Map PXR40 Microcontroller Reference Manual Rev 1 2 4 Freescale Semiconductor...
Page 120: ...Signal Descriptions 3 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 860: ...FlexCAN Module 24 50 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 1167: ...Decimation Filter Freescale Semiconductor 28 53 PXR40 Microcontroller Reference Manual Rev 1...
Page 1168: ...Decimation Filter 28 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
