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FlexRay Communication Controller (FLEXRAY)
22-90
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
22.6.5.2.2
Data Field Offset Description
Data Field Offset Content
For a detailed description of the Data Field Offset, see
Section 22.6.2.1.2, Data Field Offset
Data Field Offset Access
The application shall program the Data Field Offset when configuring the message buffers either in the
POC:config
state or when the message buffer is disabled.
22.6.5.2.3
Slot Status Description
The slot status is a read-only structure for the application and a write-only structure for the controller. The
meaning and content of the slot status in the message buffer header field depends on the message buffer
type.
Receive Message Buffer and Receive FIFO Slot Status Description
This section describes the slot status structure for the individual receive message buffers and receive
FIFOs. The content of the slot status structure for receive message buffers depends on the message buffer
type and on the channel assignment for individual receive message buffers as given by
.
The meaning of the bits in the slot status structure is explained in
.
PLDLEN
Payload Length — This field is checked and used as described in
HDCRC
Header CRC — This field provides the value of the
Header CRC
field for the frame transmitted from the message
buffer.
Table 22-87. Receive Message Buffer Slot Status Content
Receive Message Buffer Type
Slot Status Content
Individual Receive Message Buffer assigned to both channels
MBCCSRn[CHA]=1 and MBCCSRn[CHB]=1
see
Individual Receive Message Buffer assigned to channel A
MBCCSRn[CHA]=1 and MBCCSRn[CHB[=0
see
Individual Receive Message Buffer assigned to channel B
MBCCSRn[CHA]=0 and MBCCSRn[CHB]=1
see
Receive FIFO Channel A Message Buffer
see
Receive FIFO Channel B Message Buffer
see
Table 22-86. Frame Header Field Descriptions (Transmit Message Buffer) (continued)
Field
Description
Summary of Contents for PXR4030
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