Freescale Semiconductor PXR4030, Reference Manual

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Enhanced Direct Memory Access Controller (eDMA)
Freescale Semiconductor 21-43
PXR40 Microcontroller Reference Manual, Rev. 1
temporarily stored in the data path module until it is gated onto the system bus during the destination write.
This source read/destination write processing continues until the inner minor byte count has been
transferred. The eDMA done handshake signal is asserted at the end of the minor byte count transfer.
Figure 21-26. eDMA Operation, Part 2
After the inner minor byte count has been moved, the final phase of the basic data flow is performed. In
this segment, the address path logic performs the required updates to certain fields in the channel’s TCD;
for example, SADDR, DADDR, CITER. If the outer major iteration count is exhausted, then there are
additional operations performed. These include the final address adjustments and reloading of the BITER
field into the CITER. Additionally, assertion of an optional interrupt request occurs at this time, as does a
possible fetch of a new TCD from memory using the scatter-gather address pointer included in the
descriptor. The updates to the TCD memory and the assertion of an interrupt request are shown in
Figure 21-27 .
Sl
a
v
e in
te
rf
ac
e
eDMA
eDMA interrupt request
System bus
Program model/
Slave write data
Slave write address
Bus write data
Slave read data
Bus address
eDMA engine
TCD0
TCD n – 1*
eDMA peripheral
Bus read data
channel arbitration
request
SRAM
Transfer control descriptor
(TCD)
SRAM
Data path
Control
Address
path
eDMA done handshake
*n = 32 (64 for eDMA_A) channels