HV100 Series High Performance Current Vector Inverter
93
When the inverter DC braking runs, it outputs indication signal. For DC brake setting, please refer to function codes 01.00 ~
01.12.
28: Flux braking action
When the inverter runs the flux braking, it outputs indication signal. For flux braking setting, please refer to function
codes 01221.
29: Torque in limit
When the control mode is torque control, an indication signal is output. For details of torque control, please refer to group
04.10 ~ 04.23 parameter description.
30: Over-torque indication
The inverter is set according to 04.22 ~ 04.24, and outputs corresponding indication signals.
31: Auxiliary motor 1
32: Auxiliary motor 2
Terminal function of auxiliary motor 1 and 2 cooperate with process PID function module, that will realize simple
constant pressure water-supply function in one drive to control three motor.
33: The accumulated running time has arrived
When the inverter running limit time (12.11) reached, it outputs indication signal.
34 ~ 49: multi-speed or simple PLC operation segment number indication
Items 34 ~ 49 of the output terminal function respectively correspond to the 0 ~ 15 segments of multi-speed or simple
PLC . When the corresponding segment number, which is set by the output terminal, has arrived, then the inverter outputs
an indication signal.
50
：
Inverter operation indication
When the inverter is in the forward or reverse running state, it outputs indication signal.
51: Temperature arrival indication
When the actual temperature (D-33 ~ D-34) is higher than the temperature detection limit (10.14), the inverter outputs
an indication signal.
52: indication of Inverter shutdown or zero speed running
53
～
54
：
Reservation
55: communication settings
Please refer to the communication protocol.
56:Inverter operation in ready 2
It has the same function as the above No.14 (Inverter operation in ready 1), except that when the inverter is running, it
outputs an indication signal.
57: AI1 input overrun
When the value of analog input AI1 is greater than 06.53(AI1 input voltage protection upper limit) or less than
06.54(AI1 input voltage protection lower limit), an indication signal is output.
58
：
output current is beyond the limit
59: Interlock 1 Output
60: Interlock 2 Output
61: Interlock 3 Output
62: Output when frequency and current detection level arrive at the same time
When the output frequency of the inverter rises higher than the set value of FDT1 level setting (07.25), and the output
current reaches the set value of 10.23, it outputs an valid signal (open collector signal, which will become low level after the
resistor is pulled up). While the output frequency drops below FDT1 signal (set value-hysteresis value), or the output
current is less than the set value of 10.23, it outputs an invalid signal (high impedance state).
07.22
Effective logic setting of output terminal (Y1
～
Y2)
0
～
3H
0
Bit0: valid logic definition of Y1 terminal
Bit1: valid logic definition of Y2 terminal
0: indicates positive logic, that is valid for connection between Yi terminal and common terminal, and is invalid for
disconnection.
1: means anti-logic, that is invalid for connection between Yi terminal and common terminal is invalid, and valid for
disconnection.
When 07.22=0, is valid for connection between terminals Y1, Y2 and the common terminal, while invalid for
disconnection.
When 07.22=1, is invalid for connection between Y1 terminal and common terminal, but the opposite is valid; while
invalid for connection between Y2 terminal and common terminal, but disconnection is valid
When 07.22=2, is valid for connection between Y1 terminal and common terminal, but the opposite is invalid; while
invalid for connection between Y2 terminal and common terminal, but disconnection is valid
When 07.22=3,is invalid for connection between terminals Y1, Y2 and the common terminal, while valid for
disconnection.
07.23
The frequency reaches the FAR detection width
0.0 ~ 100.0% * [00.12] maximum frequency
100.0%
This function is a supplementary explanation to the function No.6 of function code 07.18 ~ 07.21. When the output
frequency of the inverter is within the positive and negative detection width of the set frequency, the terminal outputs an
valid signal (open collector signal, which is low level after the resistance is pulled up). As shown in the figure below:
