HV100 Series High Performance Current Vector Inverter
92
12
：
Output of counter detection signal
When the count detection value arrives, an indication signal is output, and it is not cleared until the count reset value
arrives. Please refer to the description of function code 07.33.
13: Counter reset signal output
When count reset value arrives, the indicator signal is output, please refer to the description of function code 07.32.
14:Inverter operation in ready 1
When the power-on is ready, that is, the inverter is trouble-free, the bus voltage is normal, the inverter forbidden
terminal is invalid, and the operation instruction can be directly accepted for starting (excluding the inverter operation), then
the terminal outputs an indication signal.
15: Programmable multi-speed operation is completed in one cycle
The programmable multi-speed (PLC) outputs an valid pulse signal with a signal width of 500mS after one cycle
operation.
16: The programmable multi-speed stage operation is completed
After the current operation stage of programmable multi-speed (PLC) is completed, an valid pulse signal is output with
a signal width of 500mS.
17: upper limit and lower limit of swing frequency
After selecting the swing frequency function, if the frequency fluctuation range of the swing frequency, calculated by
the center frequency, exceeds the upper limit frequency F00.13 and falls below the lower limit frequency 00.14 , there is
output an signal. As shown in the figure below:
Swing frequency exceeds the upper and lower limit
Figure F7-6 Schematic diagram of swing frequency amplitude limitation
18: Current limit in operation
It is the output signal when the inverter is in a current limit . Please refer to the description of function codes 10.06 ~
10.08 for current limit protection settings.
19: Overvoltage stall in operation
It is the signal output when the inverter is in overvoltage stall operation. Please refer to the description of function
code 10.04 for setting of overvoltage stall protection.
20: Undervoltage block and stop
When the DC bus voltage is lower than the undervoltage limit level, there is an indication signal.
Notes:
When the Bus is under-voltage during shutdown, digital tube displays “PoFF”
；
When the bus is under-voltage during
operation, if 10.02=0, the digital tube displays “PoFF”; if 10.02=1, the digital tube displays E-07 in fault, and the warning
indicator lights up at the same time.
21 Sleeping State
When the inverter is in the sleep state, the inverter will output indication signal.
22: Alarm signal of inverter
If there are the cases in the inverter of PID disconnection, RS485 communication failure, panel communication failure,
EEPROM reading and writing failure, encoder disconnection, etc., the inverter will output an indication signal.
23
：
AI1
＞
AI2
When the analog input AI1
＞
AI2, the inverter outputs the indication signal. Please refer to 06.05 ~ 06.11 parameter
description for details of analog input.
24: Output when length reach
When the actual length (09.69) is greater than or equal to the set length (09.68), an indication signal is output. The
length counting terminal DI6 is set to function No.47.
25: Timing time arrives
When the actual timing time is ≥ 07.36 (set timing time), the inverter will output the indication signal.
26: Dynamic braking action
When the inverter dynamic braking runs, it outputs indication signal. Please refer to the function code 12.00 ~ 12.03
for the setting of dynamic braking function.
27: DC brake action
Upper limit frequency
Lower limit frequency
Center frequency of swing frequency
