HV100 Series High Performance Current Vector Inverter
101
08.17
Sleep delay time
0.0
~
600.0S
100.0
08.18
Wake delay time
0.0
~
600.0S
5.0
08.19
Proportional gain KP2
0.01
~
100.00s
5.00
08.20
Integration time Ti2
0.01
~
10.00s
0.05
08.21
Differential time Td2
0.01
~
10.00s
0.00
08.22
Upper limit cut-off frequency of PID
【
08.23
】~
300.00Hz
50.00
08.23
Lower limit cut-off frequency of PID
-300.00Hz
~【
08.22
】
0.00
08.24
Sleep frequency
0.00Hz
~【
00.13
】
0.00
009 group-simple PLC, multi-speed
09.00
Selection of PLC operation mode
0
~
3
0
0: Stop after single cycle
The inverter stops automatically after completing a single cycle, and it needs to give the running command again
before starting. If the running time of a certain stage is 0, the running time skips the stage and goes directly to the next
stage. As shown in the figure below:
RUN command
Fig. F9-1 Schematic diagram of PLC shutdown after single cycle
1: Keep the final value running after a single cycle
After completing a single cycle, the inverter automatically keeps the running frequency and direction of the last section to
keep running. As shown in the figure below:
PLC command