HV100 Series High Performance Current Vector Inverter
39
07.25
FDT1 level set
0.00Hz
~
【
00.13
】
50.00
○
07.26
FDT1 lag value
0.0
~
100.0
%
*
【
07.25
】
2.0%
○
07.27
FDT2 detection
mode
0: Frequency set value
1: Frequency test value
0
~
1
0
○
07.28
FDT2 level set
Refer to 07.25 ~ 07.26 schematic diagram.
0.00Hz
~
【
00.13
】
25.00
○
07.29
FDT2 lag value
0.0
~
100.0
%
*
【
07.28
】
4.0%
○
07.30
Counter reach
0: Stop counting, stop output
1: Stop counting, continue to output
2: Cycle counting, stop output
3: Cycle counting, continue to output
0
~
3
3
×
07.31
Counter start
condition
0: Always start after power-on
1: Start when running, stop when stopping
0
~
1
1
×
07.32
Counter reset
value setting
This function code defines the count reset value and
detection value of the counter. When the count value of
the counter reaches the value set by function code
11.21, the corresponding multi-function output terminal
(counter reset signal output) outputs an effective signal
and clears the counter.
【
07.33
】~
65535
0
○
07.33
Counter detection
value setting
0
~【
07.32
】
0
○
07.34
Timing time reach
0: Stop timing, stop output
1: Stop timing, continue to output
2: Cycle timing, stop output
3: Cycle timing, continue to output
0
~
3
3
×
07.35
Timing start
0: Always start
1: Run start Stop stop
0
~
1
1
×
07.36
Timing timer
Set Timing timer
0
~
65535s
0
○
07.37
Y1 OFF delay time
This function code defines the time delay from the
change of state of switch output terminals Y1 and Y2 and
relays R1 and R2 to the change of output.
0.0
~
100.0s
0.0
×
07.38
Y2 OFF delay time
0.0
~
100.0s
0.0
×
07.39
R1 OFF delay time
0.0
~
100.0s
0.0
×
07.40
R2 OFF delay time
0.0
~
100.0s
0.0
×