SG-2000 MANUAL
198
The SGC Building, 13737 S.E. 26th St. Bellevue, WA. 98005 USA
©1995, SGC, Inc.
TEL: (206) 746-6310 FAX: (206) 746-6384
Data Carrier Detect (DCD bar, pin 23) is the input signal corresponding to the
"carrier detect" signal which shows carrier detect from a modem. When the
DCD bar goes “high,” the ACIA stops all the receiving operation and sets the
receiving part in reset status. The IRQ bar goes “low” if interrupt enable is set,
while DCD bar is “high.” When the DCD bar goes “low,” the receiving part is
allowed to receive data. The DCD bar should be connected to ground.
IC10 is a Asynchronous 14-Stage Binary Counter and Oscillator, SN74HC4060.
A crystal oscillator is connected between pins 10 and 11. The clock frequency
can be measured at pin 9. The frequency at pin 5 = frequency pin 9 / 32. The
frequency at pin 7 = frequency pin 9 / 16.
IC15 is a Tri-State Octal D-Type Latch, 74HC373. Data is received on pins 7, 14,
8, 13, 4, 17, 3, and 18, which correspond to data lines B0 through B7
respectively. Data is output on pins 6, 15, 9, 12, 5, 16, 2, and 19 which
correspond to data lines A0 through A7 respectively.
Truth Table
IC15
AS
P11
L
L
H
B0-B7
H
L
X
A0 - A7
H
L
Qo
Outputs
Inputs
H = high
L = low
Qo = level of output before steady-state input
conditions were established.
IC16 is a 65,536-Bit Erasable Programmable Read-Only Memory, 27C64-20.
Lines A0-A7 are the address and B0-B7 are the data output lines. Data is
output when CE bar, pin 20, and OE bar, pin 22, are low. Otherwise, the
output is in a high impedance state.
IC7 is a Real-Time Clock Plus Ram (RTC), MC146818.
Pin 3
~ 4.5 Vpp @ 32.768 KHz
Chip Enable (CE bar pin 13) must be "low" for a bus cycle in which the
MC146818 is to be accessed. CE bar is not latched and must remain stable
during the cycle.
Read/Write (R/W pin 15) is used to control the direction of data. A "high" on
the Read/Write enables a read cycle and a "low" a write cycle.