Optical Systems Design OSD2524, User Manual

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OPTICAL SYSTEMS DESIGN
DOC ID: 10120001
OSD2524 OPERATOR MANUAL
PAGE 173
'S-CLK'. The serval1 has a limitation that chip port 1 cannot be nominated as source 1. On the current
boards this is port 7 (interface gi 1/7).
Serval2 NID board limitations: Port 5-12 can be configured for 100M, 1G or 2.5G speed. In 2.5G speed
mode the SyncE hardware is not able to lock, because the recovered clock output frequency does not
match the SyncE hardware's frequency options.
Priority
The priority for this clock source. Lowest number (0) is the highest priority. If two clock sources has the
same priority, the lowest clock source number gets the highest priority in the clock selection process.
SSM Overwrite
A selectable clock source Quality Level (QL) to overwrite any QL received in a SSM. If QL is not
Received in a SSM (SSM is not enabled on this port), the SSM Overwrite QL is used as if received. The
SSM Overwrite can be set to QL_NONE, indicating that the clock source is without any know quality
(Lowest compared to clock source with known quality)
Hold Off
The Hold Off timer value. Active loss of clock Source will be delayed the selected amount of time. The
clock selector will not change clock source if the loss of clock condition is cleared within this time
ANEG Mode
This is relevant for 1000BaseT ports only. In order to recover clock from port it must be negotiated to
'Slave' mode. In order to distribute clock the port must be negotiated to 'Master' mode.
This different ANEG modes can be activated on a Clock Source port:
Prefer Slave: The Port will be negotiated to 'Slave' mode if possible.
Prefer Master: The Port will be negotiated to 'Master' mode if possible.
Forced Slave: The Port will be forced to 'Slave' mode.
The selected port in 'Locked' state will always be negotiated to 'Slave' if possible.
LOCS
Signal is lost on this clock source.
SSM
If SSM is enabled and not received properly. Type of SSM fail will be indicated in the 'Rx SSM' field
WTR
Wait To Restore timer is active.
Clear WTR
Clears the WTR timer and makes this clock source available to the clock selection process.
CLOCK SELECTION MODE AND STATE
The Clock Selector is only in one instance - the one who selects between the nominated clock sources.
Mode
The definition of the 'best' clock source is firstly the one with the highest (QL) and secondly (the ones
with equal QL) the highest priority.
Clock Selector can be in different modes:
Manual: Clock selector will select the clock source stated in Source (see below). If this manually
selected clock source is failing, the clock selector will go into holdover state.