HP AE370A - Brocade 4Gb SAN Switch 4/12, Administrator'S Manual

Page: 251 / 447

Fabric OS 5.2.x administrator guide 251
Displaying mode register bit settings
The mode register bits are described in Table 54
The
ficoncupshow modereg
command displays the mode register bit settings for the switch. A display
of 0 indicates that the mode register bit is set to off; 1 indicates that the bit is set to on.
The command format is:
ficoncupshow modereg [ bitname ]
where
bitname
is one of the mode register bits described in Table 54 .
To display all mode register bit settings for the switch:
To display the mode register bit HCP for the switch:
Table 54 FICON CUP mode register bits
POSC Programmed offline state control. When this bit is set on, the host is prevented
from taking the switch offline. The default setting is 1 (on).
UAM User alert mode. When this bit is set on, a warning is issued when an action is
attempted that will write CUP parameters on the switch. The default setting is
0 (off).
ASM Active=saved mode. When this bit is set on, all CUP configuration parameters
are persistent, meaning that they will be saved in nonvolatile storage in the
initial program load (IPL) file that is applied upon a cold reboot or a power
cycle. The default setting is 1 (on).
DCAM Switch clock alert mode. When this bit is set on, a warning is issued when the
date, tsClockServer
, or
tsTimeZone
commands are entered to set the
time and date on the switch. The default setting is 0 (off).
ACP Alternate control prohibited. Because the Fabric OS CLI, Web Tools, and
Fabric Manager are considered to be switch consoles, this bit has no effect on
their operation. Attempts to set CUP parameters through SNMP are denied
when this bit is set on. The default setting is 1 (on).
HCP Host control prohibited. When this bit is set on, the host is not allowed to set
CUP parameters. The default setting is 1 (on).
switch:admin> ficoncupshow modereg
POSC UAM ASM DCAM ACP HCP
------------------------------
1 0 1 0 1 0
switch:admin> ficoncupshow modereg HCP
HCP
0