External Memory Controller (EMC)
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
Freescale Semiconductor
21-95
CKE remains low, as long as the device is powered down. After CKE transitions to high, the SDRAM exits
the power-down mode.
21.5.3.3.5
Self- Refresh
To enable stop activity on the EMC (for power save or debug), and also maintain the content of the
SDRAM, the self-refresh mode is supported. The self-refresh mode is invoked by issuing a self-refresh
command to the SDRAM. The EMC applies the same timing as for the auto-refresh, but also pulls
SDRAM CKE (LCKE) low in the same cycle. This can only be done if all banks are idle; the SDRAM
machine must precharge them ahead of this. As long as CKE stays low, the device refreshes itself and does
not need to see any refreshes from the EMC. To exit self-refresh, CKE simply has to be pulled high. Note
that after returning from self-refresh mode the SDRAM needs a supplier-specific time before it can accept
new commands, and the auto-refresh mechanism has to be started again.
shows this timing.
The SDRAM controller always uses 200 EMC clocks, which should satisfy any SDRAM requirements.
See
Section 21.4.3.3, “JEDEC-Standard SDRAM Interface Commands
,” for SDRAM interface
commands and information on the self-refresh command.
Figure 21-56. SDRAM Self-Refresh Mode Timing
21.5.3.3.6
SDRAM Timing
To allow for very high speeds on the memory bus, the capacitive loading on the EMC must be taken into
consideration.
CLK
CKE
CS
RAS
CAS
WE
ADDR
Supplier-specific
minimum time
New command
can occur here
Self-refresh Exit
Self-refresh Entry
All banks idle
NOP
Stable clock