External Memory Controller (EMC)
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
Freescale Semiconductor
21-57
21.4.3.2
SDRAM Power-On Initialization
Following a system reset, initialization software must set up the programmable parameters in the memory
controller banks registers (ORx, BRx, SDMR). After all memory parameters are configured, system
software should execute the following initialization sequence for each SDRAM device according to its
data sheet. A typical sequence is as follows:
•
Issue a PRECHARGE-ALL-BANKS command
•
Issue eight AUTO-REFRESH commands
•
Issue a MODE-SET command to initialize the mode register
The initial commands are executed by setting SDMR[OP] and accessing the SDRAM with any read or
write that hits the relevant bank.
Note that software should ensure that no memory operations begin until this process completes.
21.4.3.3
JEDEC-Standard SDRAM Interface Commands
The SDRAM machine performs all accesses to SDRAM by using JEDEC-standard SDRAM interface
commands. The SDRAM device samples the command and data inputs on the rising edge of the bus clock.
Data at the output of the SDRAM device is sampled on the rising edge of the bus clock.
The following SDRAM interface commands are provided by setting SDMR[OP] to a nonzero value
(SDMR[OP] = 000 sets normal read/write operation):
Table 21-70. SDRAM Interface Commands
(SDMR[OP])
Command
Description
110
ACTIVATE
Latches the row address and initiates a memory read of that row. Row data is latched in
SDRAM sense amplifiers and must be restored with a PRECHARGE command before
another ACTIVATE is issued.
011
MODE-SET
Allows setting of SDRAM options—CAS latency and burst length. CAS latency depends
on the SDRAM device used. Although some SDRAMs provide burst lengths of 1, 2, 4,
8, or a page, the EMC supports only 8-beat bursts.
The EMC does not support burst lengths of 1, 2 and a page for SDRAMs. The mode
register data (CAS latency and burst length) is programmed into the SDMR register by
initialization software after reset. After the SDMR is set, the EMC transfers the
information to the SDRAM device by issuing a MODE-SET command.
100: single bank
101: all-banks
PRECHARGE
Restores data from the sense amplifiers to the appropriate row in the SDRAM device
array. Also initializes the sense amplifiers to prepare for activating another row in the
SDRAM device. Note that the EMC uses LSDA10 to distinguish between
PRECHARGE-ALL-BANKS (LSDA10 is high) and PRECHARGE-SINGLE-BANK
(LSDA10 is low). The SDRAMs must be compatible with this format.
111
READ
Latches the column address and transfers data from the selected sense amplifier on the
SDRAM device, to the output buffer as determined by the column address. During each
successive clock, additional data is driven without additional read commands. At the end
of the burst, the page remains open. Burst length is the one set for this bank. Read data
is discarded by the EMC.
