Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
21-6
Freescale Semiconductor
External Memory Controller (EMC)
LA[2:0]
O External memory non-multiplexed address LSBs
State
Meaning
Asserted/Negated—Even though the EMC shares an address and data bus, up to three least
significant bits of the RAM address always appear on the dedicated address pins, LA[2:0].
These bits may be used, unlatched, in place of LAD[2:0] to connect the three least significant
bits of the address for address phases. For some RAM devices, such as fast-page DRAM,
LA[2:0] serves as the column address offset during a burst access.
Timing
N/A
LAD[23:0]
I/O Multiplexed address and data bus
State
Meaning
Asserted/Negated—LAD[23:0] is the shared 24-bit address and data bus through which
external RAM devices transfer data and receive addresses.
Timing
Assertion/Negation—During assertion of LALE, LAD[23:0] are driven with the RAM address for
the access to follow. External logic should propagate the address on LAD[23:0] while LALE is
asserted, and latch the address upon negation of LALE.
After LALE is negated, LAD[23:0] are either driven by write data or are made high-impedance
by the EMC to sample read data driven by an external device. Following the last data transfer
of a write access, LAD[23:0] are again taken into a high-impedance state.
LCKE
O External memory clock enable
State
Meaning
Asserted/Negated—LCKE is the bus clock enable signal (CKE) for JEDEC-standard SDRAM
devices. This signal is asserted during normal SDRAM operation.
LCLK
O External memory clocks
State
Meaning
Asserted/Negated—LCLK drive external memory clock signal. If the EMC Phase-Locked Loop
(PPLL) is enabled (see CRR[DBYP],
), the bus clock phase is shifted earlier than
transitions on other EMC signals (such as LAD[23:0] and LCSx) by a time delay matching the
delay of the PPLL timing loop set up between LSYNC_OUT and LSYNC_IN.
LSYNC_OUT
O PPLL synchronization out
State
Meaning
Asserted/Negated—A replica of the bus clock (appearing on LSYNC_OUT) that should be
propagated through a passive timing loop and returned to LSYNC_IN for achieving correct
PPLL lock.
Timing
Assertion/Negation—The time delay of the timing loop should be such that it compensates for
the round-trip flight time of LCLK and clocked drivers in the system. No load other than a timing
loop should be placed on LSYNC_OUT.
LSYNC_IN
I
PPLL synchronization in
State
Meaning
Asserted/Negated—See the description of LSYNC_OUT (previous item in this table).
Table 21-2. Detailed Signal Descriptions (Continued)
Signal
I/O
Description
