External Memory Controller (EMC)
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
Freescale Semiconductor
21-73
When CRR[CLKDIV] = 4 or 8, the CSTx bits determine the state of UPM signals LCSx at each quarter
phase of the bus clock.
When CRR[CLKDIV] = 2, CST2 and CST4 are ignored and the external signal has the values defined by
CST1 and CST3 but extended to half the clock cycle in duration.
describes RAM word fields.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
CST1 CST2 CST3 CST4
Reserved
G0L
G0H
G1T1 G1T3 G2T1 G2T3
W
Reset
0000_0000_0000_0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
G3T1 G3T3
G4T1
DLT3
G4T3
WAEN G5T1 G5T3
REDO
LOOP EXEN
AMX
NA
UTA TODT LAST
W
Reset
0000_0000_0000_0000
Offset
Figure 21-40. RAM Word Field Descriptions
Table 21-72. RAM Word Field Descriptions
Bits
Name
Description
31
CST1
Chip select timing 1.
Defines the state (0 or 1) of LCSx during bus clock quarter phase 1 if CRR[CLKDIV] = 4 or 8.
Defines the state (0 or 1) of LCSx during bus clock half phase 1 if CRR[CLKDIV] = 2.
30
CST2
Chip select timing 2.
Defines the state (0 or 1) of LCSx during bus clock quarter phase 2 if CRR[CLKDIV] = 4 or 8. Ignored
when CRR[CLKDIV] = 2.
29
CST3
Chip select timing 3.
Defines the state (0 or 1) of LCSx during bus clock quarter phase 3 if CRR[CLKDIV] = 4 or 8. Defines
the state (0 or 1) of LCSx during bus clock half phase 2 if CRR[CLKDIV] = 2.
28
CST4
Chip select timing 4.
Defines the state (0 or 1) of LCSx during bus clock quarter phase 4.if CRR[CLKDIV] = 4 or 8. Ignored
when CRR[CLKDIV] = 2.
27–24
--
Reserved
23–22
G0L
General purpose line 0 lower. Defines the state of LGPL0 during the bus clock quarter phases 1 and 2
(first half phase).
00 Value defined by MxMR[G0CL]
01 Reserved
10 0
11 1