Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
21-42
Freescale Semiconductor
External Memory Controller (EMC)
21.4.1.4
Data Buffer Control (LBCTL)
The memory controller provides a data buffer control signal for the EMC data buffer control (LBCTL).
LBCTL is activated when a GPCM or UPM controlled bank is accessed. LBCTL can be disabled by setting
ORx[BCTLD]. Access to an SDRAM machine controlled bank does not activate the LBCTL control. The
LBCTL control can be further configured by BCR[BCTLC] to act as an extra LWE or an extra LOE signal
when in GPCM mode.
If LBCTL is configured as a data buffer control (BCR[LBCTLC] = 00), LBCTL is asserted (high) on the
rising edge of the bus clock on the first cycle of the memory controller operation, coincident with LALE.
If the access is a write, LBCTL remains high for the whole duration. However, if the access is a read,
LBCTL is negated (low) with the negation of LALE so that the memory device is able to drive the bus. If
back-to-back read accesses are pending, LBCTL is asserted (high) one bus clock cycle before the next
transaction starts (that is, one bus clock cycle before LALE) to allow a whole bus cycle for the bus to turn
around before the next address is driven.
If an external bus transceiver is used, LBCTL should be used to signify the write direction when high. Note
that the default (reset and bus idle) value of LBCTL is also high.
21.4.1.5
Bus Monitor
A bus monitor is provided to ensure that each bus cycle is terminated within a reasonable period
(user-defined). When a transaction starts, the bus monitor starts counting down from the time-out value
(LBCR[BMT]) until a data beat is acknowledged on the bus. The bus monitor then reloads the time-out
value and resumes the count down until the data tenure is completed, and then idles if there is no pending
transaction. Bus monitor error reporting through TESR[BM] can be disabled by setting the TEDR[BMD]
bit. However, even if bus monitor error reporting is disabled, the bus monitor is still active and can generate
a UPM exception, or even terminate a GPCM access.
It is important to ensure that the value of BCR[BMT] is not set too low; otherwise spurious bus time-outs
may occur during normal operation—particularly for SDRAMs— resulting in incomplete data transfers.
Accordingly, apart from the reset value of 0x00 (corresponding with the maximum time-out of 2048 bus
cycles), BCR[BMT] must not be set below 0x05 (or 40 bus cycles for time-out) under any circumstances.
21.4.2
General-Purpose Chip-Select Machine (GPCM)
The GPCM allows a minimal glue logic and flexible interface to SRAM, EPROM, FEPROM, ROM
devices, and external peripherals. The GPCM contains two basic configuration register groups—BRx and
ORx.
shows a simple connection between an 24-bit port size SRAM device and the EMC in GPCM
mode. Write-enable signals (LWE) are available for entire 24-bit word written to memory. Also, the output
enable signal (LOE) is provided to minimize external glue logic. On system reset, a global (boot)
chip-select is available that provides a boot ROM chip-select (LCS0) prior to the system being fully
configured.
