Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
5-12
Freescale Semiconductor
Core Configuration
Figure 5-7. Core-1 Interrupt Priority Register C1
Figure 5-8. Core-1 Interrupt Priority Register P1
Table 5-10. Interrupt Sources Priorities within an IPL
Priority Level
Interrupt Source
Group
Level 3 (non-maskable)
Highest
RESET
Stack Error
Illegal Instruction
Debug Request Interrupt
Trap
Non-Maskable Interrupt (NMI) from External
DMA Stall Interrupt
Lowest
Inter-Core Non-Maskable Interrupt (from the other core)
Level 0-2 (maskable)
D6L0
D6L1
D7L0
D7L1
0
1
2
3
4
5
6
7
8
9
10
11
DMA1 ch6 IPL
DMA1 ch7 IPL
13
12
14
15
16
17
18
19
20
21
22
23
Reserved
Reserved
0
1
2
3
4
5
6
7
8
9
10
11
13
12
14
15
16
17
18
19
20
21
22
23
STIL10
STIL11
Reserved
Reserved
Core-1
Always-On
INT IPL