Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
21-58
Freescale Semiconductor
External Memory Controller (EMC)
21.4.3.4
Page Hit Checking
The SDRAM machine supports page-mode operation. Each time a page is activated on the SDRAM
device, the SDRAM machine stores its address in a page register. The page information, which the user
writes to the ORx register, is used along with the bank size to compare page bits of the address to the page
register each time a bus-cycle access is requested. If a match is found, together with a bank match, the bus
cycle is defined as a page hit. An open page is automatically closed by the SDRAM machine if the bus
becomes idle, unless ORx[PMSEL] = 1.
21.4.3.5
Page Management
The EMC is capable of managing a maximum of 4 open pages (one page per SDRAM bank) for a single
SDRAM device. After a page is opened, the page remains open unless:
•
the next access is to a page in a different SDRAM device,
in which case all open pages on the current device are closed with a PRECHARGE-ALL-BANKS
command.
•
the next access is to a page in an SDRAM bank which has a different page open on it,
in which case the old page is closed with a PRECHARGE-SINGLE-BANK command.
•
the current SDRAM device requires refresh services,
in which case all open pages on the current device are closed with a PRECHARGE-ALL-BANKS
command.
•
the bus becomes idle and ORx[PMSEL] = 0,
in which case all open pages in the current device are closed with a PRECHARGE-ALL-BANKS
command.
111
WRITE
Latches the column address and transfers data from the data signals to the selected
sense amplifier on the SDRAM device, as determined by the column address. During
each successive clock, additional data is transferred to the sense amplifiers from the
data signals without additional write commands. At the end of the burst, the page
remains open. Burst length is the one set for this bank.
LSDDQM are inactive and write
data is undefined.
001
AUTO-REFRESH Causes a row to be read in all memory banks as determined by the refresh row address
counter. The refresh row address counter is internal to the SDRAM device. After being
read, a row is automatically rewritten into the memory array.
All banks must be in a precharged state before executing refresh.
010
SELF-REFRESH Allows data to be retained in the SDRAM device, even when the rest of the EMC is in a
power-saving mode with the clocks turned off. When placed in this mode, the SDRAM
device is capable of issuing its own refresh commands, without external clocking from
the EMC, and the LCKE pin from EMC is deasserted.
This command can be issued at any time. Normal operation can be resumed only by
setting SDMR[OP] = 000, and waiting a minimum of 200 bus cycles before issuing reads
or writes to EMC.
Table 21-70. SDRAM Interface Commands (Continued)
(SDMR[OP])
Command
Description
